[PDF] Thermal Management Of Three Dimensional Integrated Circuits Using Inter Layer Liquid Cooling eBook

Author : Calvin R. King (Jr)
Publisher :
Page : pages
File Size : 44,65 MB
Release : 2012
Category : Heat
ISBN :

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Heat removal technologies are among the most critical needs for three-dimensional (3D) stacking of high-performance microprocessors. This research reports a 3D integration platform that can support the heat removal requirements for 3D integrated circuits that contain high-performance microprocessors in the 3D stack. :This work shows the use of wafer-level batch fabrication to develop advanced electrical and fluidic three-dimensional interconnect networks in a 3D stack. Fabrication results are shown for the integration of microchannels and electrical through-silicon vias (TSVs). A compact physical model is developed to determine the design trade-offs for microchannel heat sink and electrical TSV integration. An experimental thermal measurement test-bed for evaluating a 3D inter-layer liquid cooling platform is developed. Experimental thermal testing results for an air-cooled chip and a liquid-cooled chip are compared. Microchannel heat sink cooling shows a significant junction temperature and heat sink thermal resistance reduction compared to air-cooling. The on-chip integrated microchannel heat sink, which has a thermal resistance of 0.229 °C/W, enables cooling of>100W/cm2 of each high-power density chip, while maintaining an average junction temperature of less than 50°C. Cooling liquid is circulated through the 3D stack (two layers) at flow rates of up to 100 ml/min. :The ability to assemble chips with integrated electrical and fluidic I/Os and seal fluidic interconnections at each strata interface is demonstrated using three assembly and fluidic sealing techniques. Assembly results show the stacking of up to four chips that contain integrated electrical and fluidic I/O interconnects, with an electrical I/O density of ~1600/cm2.

Author : Paul D. Franzon
Publisher : John Wiley & Sons
Page : 582 pages
File Size : 45,13 MB
Release : 2019-01-25
Category : Technology & Engineering
ISBN : 3527697063

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This fourth volume of the landmark handbook focuses on the design, testing, and thermal management of 3D-integrated circuits, both from a technological and materials science perspective. Edited and authored by key contributors from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including challenges and opportunities. The second part focuses on the test methods used to assess the quality and reliability of the 3D-integrated circuits, while the third and final part deals with thermal management and advanced cooling technologies and their integration.

Author : Yuan Xie
Publisher : Springer Science & Business Media
Page : 292 pages
File Size : 17,64 MB
Release : 2009-12-02
Category : Technology & Engineering
ISBN : 144190784X

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We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

Author : Vasilis F. Pavlidis
Publisher : Newnes
Page : 770 pages
File Size : 13,4 MB
Release : 2017-07-04
Category : Technology & Engineering
ISBN : 0124104843

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Three-Dimensional Integrated Circuit Design, Second Eition, expands the original with more than twice as much new content, adding the latest developments in circuit models, temperature considerations, power management, memory issues, and heterogeneous integration. 3-D IC experts Pavlidis, Savidis, and Friedman cover the full product development cycle throughout the book, emphasizing not only physical design, but also algorithms and system-level considerations to increase speed while conserving energy. A handy, comprehensive reference or a practical design guide, this book provides effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. Expanded with new chapters and updates throughout based on the latest research in 3-D integration: Manufacturing techniques for 3-D ICs with TSVs Electrical modeling and closed-form expressions of through silicon vias Substrate noise coupling in heterogeneous 3-D ICs Design of 3-D ICs with inductive links Synchronization in 3-D ICs Variation effects on 3-D ICs Correlation of WID variations for intra-tier buffers and wires Offers practical guidance on designing 3-D heterogeneous systems Provides power delivery of 3-D ICs Demonstrates the use of 3-D ICs within heterogeneous systems that include a variety of materials, devices, processors, GPU-CPU integration, and more Provides experimental case studies in power delivery, synchronization, and thermal characterization

Author : Sundararaman Mohanram
Publisher :
Page : 140 pages
File Size : 50,85 MB
Release : 2013
Category : Nonvolatile random-access memory
ISBN :

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"Three dimensional integrated circuits (3D-ICs) are a promising solution to the performance bottleneck in planar integrated circuits. One of the salient features of 3D-ICs is their ability to integrate heterogeneous technologies such as emerging non-volatile memories (NVMs) in a single chip. However, thermal management in 3D-ICs is a significant challenge, owing to the high heat flux (~250 W/cm2). Several research groups have focused either on run-time or design-time mechanisms to reduce the heat flux and did not consider 3D-ICs with heterogeneous stacks. The goal of this work is to achieve a balanced thermal gradient in 3D-ICs, while reducing the peak temperatures. In this research, placement algorithms for design-time optimization and choice of appropriate cooling mechanisms for run-time modulation of temperature are proposed. Specifically, an architectural framework which introduces weight-based simulated annealing (WSA) algorithm for thermal-aware placement of through silicon vias (TSVs) with inter-tier liquid cooling is proposed for design-time. In addition, integrating a dedicated stack of emerging NVMs such as RRAM, PCRAM and STTRAM, a run-time simulation framework is developed to analyze the thermal and performance impact of these NVMs in 3D-MPSoCs with inter-tier liquid cooling. Experimental results of WSA algorithm implemented on MCNC91 and GSRC benchmarks demonstrate up to 11 K reduction in the average temperature across the 3D-IC chip. In addition, power density arrangement in WSA improved the uniformity by 5%. Furthermore, simulation results of PARSEC benchmarks with NVM L2 cache demonstrates a temperature reduction of 12.5 K (RRAM) compared to SRAM in 3D-ICs. Especially, RRAM has proved to be thermally efficient replacement for SRAM with 34% lower energy delay product (EDP) and 9.7 K average temperature reduction."--Abstract.

Author : Aida Todri-Sanial
Publisher : CRC Press
Page : 409 pages
File Size : 22,74 MB
Release : 2017-12-19
Category : Technology & Engineering
ISBN : 1351830198

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Physical Design for 3D Integrated Circuits reveals how to effectively and optimally design 3D integrated circuits (ICs). It also analyzes the design tools for 3D circuits while exploiting the benefits of 3D technology. The book begins by offering an overview of physical design challenges with respect to conventional 2D circuits, and then each chapter delivers an in-depth look at a specific physical design topic. This comprehensive reference: Contains extensive coverage of the physical design of 2.5D/3D ICs and monolithic 3D ICs Supplies state-of-the-art solutions for challenges unique to 3D circuit design Features contributions from renowned experts in their respective fields Physical Design for 3D Integrated Circuits provides a single, convenient source of cutting-edge information for those pursuing 2.5D/3D technology.

Author : Rohit Sharma
Publisher : CRC Press
Page : 328 pages
File Size : 12,76 MB
Release : 2018-09-03
Category : Technology & Engineering
ISBN : 1351831593

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Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and systems, application of novel materials for 3D systems, and the thermal challenges to restrict power dissipation and improve performance of 3D systems. Containing contributions from experts in industry as well as academia, this authoritative text: Illustrates different 3D integration approaches, such as die-to-die, die-to-wafer, and wafer-to-wafer Discusses the use of interposer technology and the role of Through-Silicon Vias (TSVs) Presents the latest improvements in three major fields of thermal management for multiprocessor systems-on-chip (MPSoCs) Explores ThruChip Interface (TCI), NAND flash memory stacking, and emerging applications Describes large-scale integration testing and state-of-the-art low-power testing solutions Complete with experimental results of chip-level 3D integration schemes tested at IBM and case studies on advanced complementary metal–oxide–semiconductor (CMOS) integration for 3D integrated circuits (ICs), Design of 3D Integrated Circuits and Systems is a practical reference that not only covers a wealth of design issues encountered in 3D integration but also demonstrates their impact on the efficiency of 3D systems.

Author : Rajappa Tadepalli
Publisher :
Page : 206 pages
File Size : 12,68 MB
Release : 2007
Category :
ISBN :

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(Cont.) Deliberate pre-adhesion exposure of the Cu surfaces to 10-6 Torr O2 leads to a dramatic reduction in adhesion (to 0.1 J/m2), suggesting the formation of a Cu oxide that is detrimental to the Cu-Cu bonding process. The UHV-AFM measurements suggest that strong Cu-Cu bonds can be created by bonding clean Cu surfaces at room temperature, thereby eliminating several thermal stability issues in the thermocompression bonding process. The thermal management problem in 3D ICs containing multiple device layers was examined using an analytical model of forced liquid cooling via Cu-sealed integrated microchannels. Integration of microchannels requires a reduction in the area available for interconnects and adhesion, causing a trade-off between the inter-layer bonded area and the size and density of the channels that can be included. The optimum channel density is a function of the achievable local Cu-Cu bond strength.

Author : Madhusudan Iyengar
Publisher : World Scientific
Page : 479 pages
File Size : 44,81 MB
Release : 2024-01-10
Category : Technology & Engineering
ISBN : 9811279381

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This book is a comprehensive guide on emerging cooling technologies for processors in microelectronics. It covers various topics such as chip-embedded two-phase cooling, monolithic microfluidic cooling, numerical modeling, and advances in materials engineering for conduction-limited direct contact cooling, with a goal to remedy high heat flux issues.The book also discusses the co-design of thermal and electromagnetic properties for the development of light and ultra-high efficiency electric motors. It provides an in-depth analysis of the scaling limits, challenges, and opportunities in embedded cooling, including high power RF amplifiers and self-emissive and liquid crystal displays. Its analysis of emerging cooling technologies provides a roadmap for the future of cooling technology in microelectronics.This book is a good starting point for the electrical and thermal engineers, as well as MS and PhD students, interested in understanding and collaboratively tackling the complex and multidisciplinary field of microelectronics device (embedded) cooling. A basic knowledge of heat conduction and convection is required.

Author : Seda Ogrenci-Memik
Publisher : IET
Page : 264 pages
File Size : 44,87 MB
Release : 2015-12
Category : Computers
ISBN : 1849199345

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Heat Management in Integrated Circuits focuses on devices and materials that are intimately integrated on-chip (as opposed to in package or on-board) for the purposes of thermal monitoring and thermal management, i.e., cooling. The devices and circuits cover various designs used for the purpose of converting temperature to a digital measurement, heat to electricity, and actively biased circuits that reverse thermal gradients on chips for the purpose of cooling. The book includes fundamental operating principles that touch upon physics of materials that are used to construct sensing, harvesting, and cooling devices, which will be followed by circuit and system design aspects that enable successful functioning of these devices as an on-chip system. Finally, the author discusses the use of these devices and systems for thermal management and the role they play in enabling energy-efficient and sustainable high performance computing systems.