[PDF] Static And Dynamic Virtual Channel Allocation For High Performance In Order Communication In On Chip Networks eBook

Author : Keun Sup Shim
Publisher :
Page : 67 pages
File Size : 21,12 MB
Release : 2010
Category :
ISBN :

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Most routers in on-chip interconnection networks (OCINs) have multiple virtual channels (VCs) to mitigate the effects of head-of-line blocking. Multiple VCs necessitate VC allocation schemes since packets or flows must compete for channels when there are more flows than virtual channels at a link. Conventional dynamic VC allocation, however, raises two critical issues. First, it still suffers from a fair amount of head-of-line blocking since all flows can be assigned to any VC within a link. Moreover, dynamic VC allocation compromises the guarantee of in-order delivery even when used with basic variants of dimension-ordered routing, requiring large reorder buffers at the destination core or, alternatively, expensive retransmission logic. In this thesis, we present two virtual channel allocation schemes to address these problems: Static Virtual Channel Allocation and Exclusive Dynamic Virtual Channel Allocation (EDVCA). Static VC allocation assigns channels to flows by precomputation when oblivious routing is used, and ensures deadlock freedom for arbitrary minimal routes when two or more VCs are available. EDVCA, on the other hand, is done at runtime, not requiring knowledge of traffic patterns or routes in advance. We demonstrate that both static VCA and EDVCA guarantee in-order packet delivery under single path routing, and furthermore, that they both outperform dynamic VC allocation (out-of-order) by effectively reducing head-of-line blocking. We also introduce a novel bandwidth-sensitive oblivious routing scheme (BSORM), which is deadlock-free through appropriate static VC allocation. Implementation for these schemes requires only minor, inexpensive changes to traditional oblivious dimension-ordered router architectures, more than offset by the removal of packet reorder buffers and logic.

Author : K. Ashoka Reddy
Publisher : Springer Nature
Page : 682 pages
File Size : 16,5 MB
Release : 2021-05-23
Category : Computers
ISBN : 9811600813

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This book includes selected papers presented at the 4th International Conference on Data Engineering and Communication Technology (ICDECT 2020), held at Kakatiya Institute of Technology & Science, Warangal, India, during 25–26 September 2020. It features advanced, multidisciplinary research towards the design of smart computing, information systems and electronic systems. It also focuses on various innovation paradigms in system knowledge, intelligence and sustainability which can be applied to provide viable solutions to diverse problems related to society, the environment and industry.

Author : Adnan Ahmad
Publisher :
Page : pages
File Size : 14,63 MB
Release : 2017
Category :
ISBN :

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Network-on-Chip(NoC) is the communication backbone in domain of of multi-core processor systems. As the number of cores in conventional bus based architecture is increasing communication techniques are becoming ineffective and complex. Wormhole flow control is the most commonly used flow control algorithm in NoC. However as the work load is increased in the NoC wormhole flow control causes head-of-line blocking which results in contention for the physical channel. This issue can be resolved by using virtual channel flow control. In this work we investigate the effect of input-queued Virtual Channels router model on the performance of NoC by varying different parameters like injection rate and the packet length. We simulate K-ary-n cubes mesh topology with dimension order routing (DOR) under synthetic workloads in order to find the effect of virtual channels on the performance of Mesh network in term of throughput and latency. We show that as the number of virtual channels is increased there is an improvement in the throughput and latency of the network up to a certain number of virtual channels beyond which the network reaches saturated state. Our work can be used as a guidance to find the optimal number of virtual channels for a given NoC configuration and traffic parameters.

Author : Sungho Park
Publisher :
Page : pages
File Size : 41,46 MB
Release : 2010
Category :
ISBN :

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As the feature size is continuously decreasing and integration density is increasing, interconnections have become a dominating factor in determining the overall quality of a chip. Due to the limited scalability of system bus, it cannot meet the requirement of current System-on-Chip (SoC) implementations where only a limited number of functional units can be supported. Long global wires also cause many design problems, such as routing congestion, noise coupling, and difficult timing closure. Network-on-Chip (NoC) architectures have been proposed to be an alternative to solve the above problems by using a packet-based communication network. The processing elements (PEs) communicate with each other by exchanging messages over the network and these messages go through buffers in each router. Buffers are one of the major resource used by the routers in virtual channel flow control. In this thesis, we analyze two kinds of buffer allocation approaches, static and dynamic buffer allocations. These approaches aim to increase throughput and minimize latency by means of virtual channel flow control. In statically allocated buffer architecture, size and organization are design time decisions and thus, do not perform optimally for all traffic conditions. In addition, statically allocated virtual channel consumes a waste of area and significant leakage power. However, dynamic buffer allocation scheme claims that buffer utilization can be increased using dynamic virtual channels. Dynamic virtual channel regulator (ViChaR), have been proposed to use centralized buffer architecture which dynamically allocates virtual channels and buffer slots in real-time depending on traffic conditions. This ViChaR0́9s dynamic buffer management scheme increases buffer utilization, but it also increases design complexity. In this research, we reexamine performance, power consumption, and area of ViChaR0́9s buffer architecture through implementation. We implement a generic router and a ViChaR architecture using Verilog-HDL. These RTL codes are verified by dynamic simulation, and synthesized by Design Compiler to get area and power consumption. In addition, we get latency through Static Timing Analysis. The results show that a ViChaR0́9s dynamic buffer management scheme increases the latency and power consumption significantly even though it could increase buffer utilization. Therefore, we need a novel design to achieve high buffer utilization without a loss.

Author : Wei Song
Publisher : CRC Press
Page : 381 pages
File Size : 40,74 MB
Release : 2022-05-10
Category : Computers
ISBN : 1000578828

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Asynchronous On-Chip Networks and Fault-Tolerant Techniques is the first comprehensive study of fault-tolerance and fault-caused deadlock effects in asynchronous on-chip networks, aiming to overcome these drawbacks and ensure greater reliability of applications. As a promising alternative to the widely used synchronous on-chip networks for multicore processors, asynchronous on-chip networks can be vulnerable to faults even if they can deliver the same performance with much lower energy and area compared with their synchronous counterparts – faults can not only corrupt data transmission but also cause a unique type of deadlock. By adopting a new redundant code along with a dynamic fault detection and recovery scheme, the authors demonstrate that asynchronous on-chip networks can be efficiently hardened to tolerate both transient and permanent faults and overcome fault-caused deadlocks. This book will serve as an essential guide for researchers and students studying interconnection networks, fault-tolerant computing, asynchronous system design, circuit design and on-chip networking, as well as for professionals interested in designing fault-tolerant and high-throughput asynchronous circuits.

Author : Bo Ji
Publisher : Springer Nature
Page : 116 pages
File Size : 23,94 MB
Release : 2022-05-31
Category : Computers
ISBN : 3031792726

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The last decade has seen an unprecedented growth in the demand for wireless services. These services are fueled by applications that often require not only high data rates, but also very low latency to function as desired. However, as wireless networks grow and support increasingly large numbers of users, these control algorithms must also incur only low complexity in order to be implemented in practice. Therefore, there is a pressing need to develop wireless control algorithms that can achieve both high throughput and low delay, but with low-complexity operations. While these three performance metrics, i.e., throughput, delay, and complexity, are widely acknowledged as being among the most important for modern wireless networks, existing approaches often have had to sacrifice a subset of them in order to optimize the others, leading to wireless resource allocation algorithms that either suffer poor performance or are difficult to implement. In contrast, the recent results presented in this book demonstrate that, by cleverly taking advantage of multiple physical or virtual channels, one can develop new low-complexity algorithms that attain both provably high throughput and provably low delay. The book covers both the intra-cell and network-wide settings. In each case, after the pitfalls of existing approaches are examined, new systematic methodologies are provided to develop algorithms that perform provably well in all three dimensions.

Author : Phan Cong-Vinh
Publisher : CRC Press
Page : 286 pages
File Size : 20,86 MB
Release : 2018-09-03
Category : Computers
ISBN : 1351833715

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Despite the growing mainstream importance and unique advantages of autonomic networking-on-chip (ANoC) technology, Autonomic Networking-On-Chip: Bio-Inspired Specification, Development, and Verification is among the first books to evaluate research results on formalizing this emerging NoC paradigm, which was inspired by the human nervous system. The FIRST Book to Assess Research Results, Opportunities, & Trends in "BioChipNets" The third book in the Embedded Multi-Core Systems series from CRC Press, this is an advanced technical guide and reference composed of contributions from prominent researchers in industry and academia around the world. A response to the critical need for a global information exchange and dialogue, it is written for engineers, scientists, practitioners, and other researchers who have a basic understanding of NoC and are now ready to learn how to specify, develop, and verify ANoC using rigorous approaches. Offers Expert Insights Into Technical Topics Including: Bio-inspired NoC How to map applications onto ANoC ANoC for FPGAs and structured ASICs Methods to apply formal methods in ANoC development Ways to formalize languages that enable ANoC Methods to validate and verify techniques for ANoC Use of "self-" processes in ANoC (self-organization, configuration, healing, optimization, protection, etc.) Use of calculi for reasoning about context awareness and programming models in ANoC With illustrative figures to simplify contents and enhance understanding, this resource contains original, peer-reviewed chapters reporting on new developments and opportunities, emerging trends, and open research problems of interest to both the autonomic computing and network-on-chip communities. Coverage includes state-of-the-art ANoC architectures, protocols, technologies, and applications. This volume thoroughly explores the theory behind ANoC to illustrate strategies that enable readers to use formal ANoC methods yet still make sound judgments and allow for reasonable justifications in practice.

Author : Giovanni De Micheli
Publisher : Elsevier
Page : 408 pages
File Size : 36,25 MB
Release : 2006-08-30
Category : Technology & Engineering
ISBN : 0080473563

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The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a powerful solution. This book is the first to provide a unified overview of NoC technology. It includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions. * Leading-edge research from world-renowned experts in academia and industry with state-of-the-art technology implementations/trends * An integrated presentation not currently available in any other book * A thorough introduction to current design methodologies and chips designed with NoCs

Author : Jose Duato
Publisher : Morgan Kaufmann
Page : 626 pages
File Size : 36,17 MB
Release : 2003
Category : Computers
ISBN : 1558608524

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Foreword -- Foreword to the First Printing -- Preface -- Chapter 1 -- Introduction -- Chapter 2 -- Message Switching Layer -- Chapter 3 -- Deadlock, Livelock, and Starvation -- Chapter 4 -- Routing Algorithms -- Chapter 5 -- CollectiveCommunicationSupport -- Chapter 6 -- Fault-Tolerant Routing -- Chapter 7 -- Network Architectures -- Chapter 8 -- Messaging Layer Software -- Chapter 9 -- Performance Evaluation -- Appendix A -- Formal Definitions for Deadlock Avoidance -- Appendix B -- Acronyms -- References -- Index.

Author : Cheeneebash, Jayrani
Publisher : African Minds
Page : 82 pages
File Size : 49,50 MB
Release : 2014-12-01
Category : Technology & Engineering
ISBN : 1920677534

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The study of the channel allocation problem has received much attention during the last decade. Several techniques such as genetic algorithm, artificial neural network, simulated annealing, tabu search and others have been used. This book is devoted to compiling all the techniques that have been used to solve the channel allocation problem. Each of the methods is described fully in a manner that explains the essential parts of how the techniques are formulated and applied in solving the problem. This textbook will be helpful to students studying communications or researchers as it compiles all the techniques used since this problem was first solved.