[PDF] Reference Free Cmos Pipeline Analog To Digital Converters eBook

Author : Michael Figueiredo
Publisher : Springer Science & Business Media
Page : 189 pages
File Size : 28,23 MB
Release : 2012-08-24
Category : Technology & Engineering
ISBN : 146143467X

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This book shows that digitally assisted analog to digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low resolution reference-free high-speed time-interleaved pipeline ADC employing all mentioned design techniques and circuits is presented, implemented and experimentally characterized. This ADC is said to be reference-free because it precludes any reference voltage, therefore saving power and area, as reference circuits are not necessary. Experimental results demonstrate the potential of the techniques which enabled the implementation of area and power efficient circuits.

Author : Chen-Kai Hsu
Publisher :
Page : 0 pages
File Size : 23,84 MB
Release : 2020
Category :
ISBN :

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Pipeline analog-to-digital converters (ADCs) are typically chosen for medium-to-high-resolution and high-bandwidth applications. Nevertheless, each generation of technology scaling, strongly driven by the demand for even more powerful digital computation capabilities, continuously entails a great challenge on the precision of the interstage gain in pipeline ADCs. The inaccurate interstage gain leads to the quantization leakage error in pipeline ADCs, which degrades the signal-to-noise-and-distortion ratio (SNDR) of pipeline ADCs. This dissertation demonstrates three techniques to address the inaccurate interstage gain in pipeline ADCs. To start with, an interstage gain error shaping (GES) technique is proposed. It can substantially suppress the in-band quantization leakage error in pipeline ADCs. It works for both closed-loop and open-loop amplification. It does not require extra clock phases, long convergence time, or an interruption of the digitization, incur large power or area overhead, or pose a constraint on the input signal. A two-stage pipeline successive-approximation-register (SAR) ADC equipped with the proposed second-order GES technique in 40-nm low-power (LP) CMOS technology achieves a 75.8-dB SNDR over 12.5-MHz bandwidth while operating at 100 MS/s and consuming 1.54 mW. It achieves a 174.9-dB Schreier figure of merit (FoM). The GES-related hardware only occupies less than 2% of the total active area. Next, an enhanced interstage GES technique that adopts a digital error feedback (DEF) method to address the truncation error in the prior implementation is proposed, which can extend the interstage gain error tolerance by five times. The proposed DEF technique does not introduce additional errors as it operates purely in the digital domain. In addition, a first-order passive quantization noise shaping (NS) technique that reduces the input-pair ratio of the two-input-pair comparator by 2.7 times is proposed. The proposed passive NS technique can alleviate the noise penalty caused by using a multiple-input-pair comparator. A two-stage pipeline SAR ADC equipped with the proposed techniques in 40-nm LP CMOS technology achieves a 77.1-dB SNDR over 6.25-MHz bandwidth while operating at 100 MS/s and consuming 1.38 mW. It achieves a 173.7-dB Schreier FoM. Finally, the use of foreground interstage gain calibration is demonstrated to address the inaccurate interstage gain in pipeline ADCs. It is implemented in a 13-bit 40-MS/s two-stage pipeline SAR ADC. The prototype ADC is designed for the phase-II readout electronics of the ATLAS liquid argon (LAr) calorimeter. To ensure its robustness under the harsh radioactive environment, several radiation-hardened techniques are implemented. To increase its yield, foreground digital-to-analog converter (DAC) mismatch calibration is also implemented. It is implemented in 65-nm LP CMOS technology. With the foreground calibration, it achieves an effective number of bits (ENOB) better than 11.2 bits over the bandwidth of interest while consuming 17.6 mW. Besides, on-chip high-speed reference buffers are deployed to avoid the need for large decoupling capacitors and provide stable reference voltages by tracking bandgap voltage references.

Author : Yun Chiu
Publisher : Springer-Verlag New York Incorporated
Page : 400 pages
File Size : 45,36 MB
Release : 2006-01-01
Category : Computers
ISBN : 9780387270395

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Presenting a treatment of the subject of the pipeline analog-to-digital converter (ADC), this book emphasizes implementation techniques using CMOS switched-capacitor circuits. The core materials of the textbook include architecture, circuit building blocks, practical limitations, consideration of precision, and calibration techniques.

Author : Weitao Li
Publisher : Springer
Page : 181 pages
File Size : 36,27 MB
Release : 2017-08-01
Category : Technology & Engineering
ISBN : 3319620126

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This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Author : Mikael Gustavsson
Publisher : Springer Science & Business Media
Page : 378 pages
File Size : 38,45 MB
Release : 2006-04-18
Category : Technology & Engineering
ISBN : 0306473054

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CMOS Data Converters for Communications distinguishes itself from other data converter books by emphasizing system-related aspects of the design and frequency-domain measures. It explains in detail how to derive data converter requirements for a given communication system (baseband, passband, and multi-carrier systems). The authors also review CMOS data converter architectures and discuss their suitability for communications. The rest of the book is dedicated to high-performance CMOS data converter architecture and circuit design. Pipelined ADCs, parallel ADCs with an improved passive sampling technique, and oversampling ADCs are the focus for ADC architectures, while current-steering DAC modeling and implementation are the focus for DAC architectures. The principles of the switched-current and the switched-capacitor techniques are reviewed and their applications to crucial functional blocks such as multiplying DACs and integrators are detailed. The book outlines the design of the basic building blocks such as operational amplifiers, comparators, and reference generators with emphasis on the practical aspects. To operate analog circuits at a reduced supply voltage, special circuit techniques are needed. Low-voltage techniques are also discussed in this book. CMOS Data Converters for Communications can be used as a reference book by analog circuit designers to understand the data converter requirements for communication applications. It can also be used by telecommunication system designers to understand the difficulties of certain performance requirements on data converters. It is also an excellent resource to prepare analog students for the new challenges ahead.

Author : Rudy J. van de Plassche
Publisher : Springer Science & Business Media
Page : 628 pages
File Size : 48,17 MB
Release : 2013-04-17
Category : Technology & Engineering
ISBN : 1475737688

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CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes in depth converter specifications like Effective Number of Bits (ENOB), Spurious Free Dynamic Range (SFDR), Integral Non-Linearity (INL), Differential Non-Linearity (DNL) and sampling clock jitter requirements. Relations between these specifications and practical issues like matching of components and offset parameters of differential pairs are derived. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes the requirements of input and signal reconstruction filtering in case a converter is applied into a signal processing system. CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters describes design details of high-speed A/D and D/A converters, high-resolution A/D and D/A converters, sample-and-hold amplifiers, voltage and current references, noise-shaping converters and sigma-delta converters, technology parameters and matching performance, comparators and limitations of comparators and finally testing of converters.

Author : Kyung Ryun Kim
Publisher : Stanford University
Page : 128 pages
File Size : 12,26 MB
Release : 2010
Category :
ISBN :

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In high-performance pipelined analog-to-digital converters (ADCs), the residue amplifiers dissipate the majority of the overall converter power. Therefore, finding alternatives to the relatively inefficient, conventional class-A circuit realization is an active area of research. One option for improvement is to employ class-AB amplifiers, which can, in principle, provide large drive currents on demand and improve the efficiency of residue amplification. Unfortunately, due to the simultaneous demand for high speed and high gain in pipelined ADCs, the improvements seen in class-AB designs have so far been limited. This dissertation presents the design of an efficient class-AB amplification scheme based on a pseudo-differential, single-stage and cascode-free architecture. Nonlinear errors due to finite DC gain are addressed using a deterministic digital background calibration that measures the circuit imperfections in time intervals between normal conversion cycles of the ADC. As a proof of concept, a 12-bit 30-MS/s pipelined ADC was realized using class-AB amplifiers with the proposed digital calibration. The prototype ADC occupies an active area of 0.36 mm2 in 90-nm CMOS. It dissipates 2.95 mW from a 1.2-V supply and achieves an SNDR of 64.5 dB for inputs near the Nyquist frequency. The corresponding figure of merit is 72 fJ/conversion-step.

Author : Pieter Harpe
Publisher : Springer
Page : 419 pages
File Size : 36,70 MB
Release : 2014-07-23
Category : Technology & Engineering
ISBN : 3319079387

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This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

Author : Ricardo Filipe Sereno Póvoa
Publisher : Springer
Page : 153 pages
File Size : 32,46 MB
Release : 2018-08-10
Category : Technology & Engineering
ISBN : 3319952072

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This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier. Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.