Author : Kai Wei
Publisher :
Page : 229 pages
File Size : 42,47 MB
Release : 2021
Category : Analog-to-digital converters
ISBN :
High-speed, broadband, and compact analog-to-digital converters (ADC) are the key components in signal waveform generation and efficient detection for future telecommunication and remote sensing applications. Canonical electronic ADCs suffers from limited effective number of bits (ENOB) at giga-sampling rate due to electronic clock aperture jitter and comparator ambiguity due to the transistor bandwidth limitations. An electrically interleaved ADC operating at lower sampling rates or a hybrid ADC using optically sampled and electrically quantized structures that leverages the low optical aperture jitter of mode-locked laser and high-resolution electronic quantization are not only power consuming but are also limited in effective sampling rate within 10 GS/s as the quantizer outputs still must be accurately aligned in time to form the input information in electronic domain. On the other hand, the reported all-optical ADC (AOADC) benefits from the low jitter of optical clock, while quantizes the input signal in optical domain using spatial modulation. In this dissertation, various design innovations leading to paths of a fully integrated 40 GS/s AOADC with 8 ENOB by incorporating integrated stable clock using self-forced optical phase modulator (PM) based opto-electronic oscillators (OEO) and single-channel spatial light modulator (SLM) by advancing research innovations of the past laboratory graduates.Design of optical PM and SLM designs are based on broadband traveling-wave coupled microstrip (CMS) electrode structures with improved phase and angular deflection modulation using slow-waveguiding behavior of 1-D photonic crystal (PhC) topologies as superstrate using optical beam propagation (OptiBPM), finite-difference-time-domain (OptiFDTD), and finite element method (HFSS). Optimized design geometries of 1-D PhC over 1550 nm is considered to minimize the optical loss while the modulation sensitivity is enhanced by about 108% compared to modulator designs without the PhC layer. Similar spatial modulation sensitivity improvements are achieved for SLMs with leaky wave designs. These designs are implemented on low-cost Si-photonics and electro-optic (E-O) chromophores on low loss and higher index PMMI host material rather than standard PMMA. Novel design of OEO based on PM rather than Mach-Zehnder modulator (MZM) has advantage of bias voltage independence that makes OEO less sensitive to shift in bias voltage due to piezo-electric or pyro-electric properties of E-O material, but then requires phase to intensity modulators (PM-IM). Sagnac-loop based OEO is demonstrated, where close-in to carrier phase noise at 10 GHz are reduced using self-forced techniques of self-injection locking and dual self-phase-locked loop (SILDPLL) for long-term stability of optical clocks to predict timing jitter as low as 19.5 fs using 3-/5-km fiber mandrills in modular experiment.To achieve a monolithically integrated AOADC consisting of the proposed SLM and stable optical clock provided by OEOs with the estimated performance, a heterogeneously integrated InP multi-mode laser (MML) as an on-chip OEO source, where inter-modal oscillation and PM-IM convertor rather than relying on Sagnac-loop design, where a non-reciprocal phase shifter (NRPS) is not compatible with Si on-chip integration at the present. RF signal generated from MML typically suffers poor stabilization and 25-fold reduction in timing jitter is measured compared to the free-running case, when SEILDPLL with external optical delays of 5-/15-(mu)s are employed. Moreover, for a fully integrated design rather than modular fiber mandrills, both non-dispersive and dispersive add-drop filter (ADF) resonators are modeled using both full-wave OptiFDTD and proven MATLAB codes on SiN based optical time delays of 975 ns within a chip area of 27 cm2 and 0.1 cm2, respectively. Furthermore, limits of performance improvements using a combined stabilization processes of self-mode-locking (SML) techniques and self-forced SML are investigated. Timing jitter of a 13-mode SML (e.g., fabricated using HHI foundry service) with 700 ns SEIL and 700-/900-ns DSPLL integrated IOEO is estimated to be only 7.6 fs at 10 GHz.