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Modeling and Simulation of High Speed VLSI Interconnects brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. Modeling and Simulation of High Speed VLSI Interconnects serves as an excellent reference, providing insight into some of the most important issues in the field.
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.
This Second Edition focuses on emerging topics and advances in the field of VLSI interconnections In the decade since High-Speed VLSI Interconnections was first published, several major developments have taken place in the field. Now, updated to reflect these advancements, this Second Edition includes new information on copper interconnections, nanotechnology circuit interconnects, electromigration in the copper interconnections, parasitic inductances, and RLC models for comprehensive analysis of interconnection delays and crosstalk. Each chapter is designed to exist independently or as a part of one coherent unit, and several appropriate exercises are provided at the end of each chapter, challenging the reader to gain further insight into the contents being discussed. Chapter subjects include: * Preliminary Concepts * Parasitic Resistances, Capacitances, and Inductances * Interconnection Delays * Crosstalk Analysis * Electromigration-Induced Failure Analysis * Future Interconnections High-Speed VLSI Interconnections, Second Edition is an indispensable reference for high-speed VLSI designers, RF circuit designers, and advanced students of electrical engineering.
As semiconductor technology advances in the ultra deep sub-micron era, on-chip global interconnections have been an ever-greater barrier to achieving high-performance and low-power for the increasingly larger system-on-chip (SoC) designs. Various on-chip interconnection schemes are proposed to tackle the scaling issue of global wires by manipulating the wire operation regions, changing signaling methods, and applying different equalization techniques. Optimization frameworks are also proposed to aid the transmitter-wire-receiver co-design based on user-defined constraints. For the six representative global interconnection schemes, we investigate their performance metrics with technology scaling by performing optimizations using the proposed SQP-based framework. A set of simple models is also developed to enable early-stage system-level analysis. Performance of different interconnection schemes are predicted and compared over several technology nodes. We further perform studies on the pipelined $RC$ interconnection by exploring its performance metrics with voltage and technology scaling based on different design objectives. A performance evaluation flow is developed to generate the optimal designs for given objectives. Also, impacts of pipelining depth, voltage and technology scaling are illustrated. Finally, we propose an energy-efficient high-speed on-chip global interconnection by employing continuous-time active equalization. Modeling and design of transmitter and receiver circuits are discussed. Analytical formula of received eye-opening is derived for system-level design planning. We further perform transmitter-receiver co-design through an optimization framework and explore the design space to generate design based on best energy-throughput tradeoff.
Modeling and Simulation of High Speed VLSI Interconnects brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. Modeling and Simulation of High Speed VLSI Interconnects serves as an excellent reference, providing insight into some of the most important issues in the field.