[PDF] On Nominal Delay Minimiza Tion In Lut Based Le Based Fpga Technology Mapping eBook

Author : Marcin Kubica
Publisher : Springer Nature
Page : 207 pages
File Size : 33,41 MB
Release : 2020-11-07
Category : Technology & Engineering
ISBN : 3030604888

GET BOOK

This book covers selected topics of automated logic synthesis dedicated to FPGAs. The authors focused on two main problems: decomposition of the multioutput functions and technology mapping. Additionally, the idea of using binary decision diagrams (BDD) in these processes was presented. The book is a scientific monograph summarizing the authors’ many years of research. As a result, it contains a large number of experimental results, which makes it a valuable source for other researchers. The book has a significant didactic value. Its arrangement allows for a gradual transition from basic things (e.g., description of logic functions) to much more complex issues. This approach allows less advanced readers to better understand the described problems. In addition, the authors made sure that the issues described in the book were supported by practical examples, thanks to which the reader can independently analyze even the most complex problems described in the book.

Author : Jason Cong
Publisher :
Page : 22 pages
File Size : 37,89 MB
Release : 1992
Category : Gate array circuits
ISBN :

GET BOOK

As the core of the area minimization step, we have developed a polynomial-time optimal algorithm for computing an area-minimum mapping solution without node duplication for a general Boolean network, which makes a significant step towards complete understanding of the general area minimization problem in FPGA technology mapping. The experimental results on MCNC benchmark circuits show that our solution sets outperform the solutions produced by many existing mapping algorithms in terms of both area and depth minimization."

Author : Jason Cong
Publisher :
Page : 29 pages
File Size : 28,80 MB
Release : 1992
Category : Gate array circuits
ISBN :

GET BOOK

A key step in our algorithm is to compute a minimum height K- feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUTs by maximizing the volume of each cut and by several post-processing operations. Based on these results, we implemented an [sic] LUT-based FPGA mapping package called Flow-Map. We tested Flow- Map on a large set of benchmark examples and compared it with other LUT- based FPGA mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. On average, Flow-Map reduces the LUT network depth by up to 8% and reduces the number of LUTs by up to 50% compared to the three previous methods."

Author : Marcin Kubica
Publisher :
Page : 0 pages
File Size : 45,77 MB
Release : 2021
Category :
ISBN : 9783030604899

GET BOOK

This book covers selected topics of automated logic synthesis dedicated to FPGAs. The authors focused on two main problems: decomposition of the multioutput functions and technology mapping. Additionally, the idea of using binary decision diagrams (BDD) in these processes was presented. The book is a scientific monograph summarizing the authors' many years of research. As a result, it contains a large number of experimental results, which makes it a valuable source for other researchers. The book has a significant didactic value. Its arrangement allows for a gradual transition from basic things (e.g., description of logic functions) to much more complex issues. This approach allows less advanced readers to better understand the described problems. In addition, the authors made sure that the issues described in the book were supported by practical examples, thanks to which the reader can independently analyze even the most complex problems described in the book.