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Author : Hossein Hashemi
Publisher : Cambridge University Press
Page : 471 pages
File Size : 40,94 MB
Release : 2016-04-04
Category : Technology & Engineering
ISBN : 1107055865
Build high-performance, energy-efficient circuits with this cutting-edge guide to designing, modeling, analysing, implementing and testing new mm-wave systems.
Author : Ali M. Niknejad
Publisher : Springer Science & Business Media
Page : 313 pages
File Size : 34,6 MB
Release : 2008-01-03
Category : Technology & Engineering
ISBN : 0387765611
This book compiles and presents the research results from the past five years in mm-wave Silicon circuits. This area has received a great deal of interest from the research community including several university and research groups. The book covers device modeling, circuit building blocks, phased array systems, and antennas and packaging. It focuses on the techniques that uniquely take advantage of the scale and integration offered by silicon based technologies.
Author : Hossein Hashemi
Publisher : Cambridge University Press
Page : 471 pages
File Size : 50,93 MB
Release : 2016-04-04
Category : Technology & Engineering
ISBN : 1316395367
Build high-performance, spectrally clean, energy-efficient mm-wave power amplifiers and transmitters with this cutting-edge guide to designing, modeling, analysing, implementing and testing new mm-wave systems. Suitable for students, researchers and practicing engineers, this self-contained guide provides in-depth coverage of state-of-the-art semiconductor devices and technologies, linear and nonlinear power amplifier technologies, efficient power combining systems, circuit concepts, system architectures and system-on-a-chip realizations. The world's foremost experts from industry and academia cover all aspects of the design process, from device technologies to system architectures. Accompanied by numerous case studies highlighting practical design techniques, tradeoffs and pitfalls, this is a superb resource for those working with high-frequency systems.
Author : Dixian Zhao
Publisher : Springer
Page : 188 pages
File Size : 32,44 MB
Release : 2015-06-29
Category : Technology & Engineering
ISBN : 3319188399
This book focuses on the development of design techniques and methodologies for 60-GHz and E-band power amplifiers and transmitters at device, circuit and layout levels. The authors show the recent development of millimeter-wave design techniques, especially of power amplifiers and transmitters, and presents novel design concepts, such as “power transistor layout” and “4-way parallel-series power combiner”, that can enhance the output power and efficiency of power amplifiers in a compact silicon area. Five state-of-the-art 60-GHz and E-band designs with measured results are demonstrated to prove the effectiveness of the design concepts and hands-on methodologies presented. This book serves as a valuable reference for circuit designers to develop millimeter-wave building blocks for future 5G applications.
Author : Jaco du Preez
Publisher : Springer
Page : 367 pages
File Size : 22,55 MB
Release : 2017-10-05
Category : Technology & Engineering
ISBN : 3319621661
This book provides a detailed review of millimeter-wave power amplifiers, discussing design issues and performance limitations commonly encountered in light of the latest research. Power amplifiers, which are able to provide high levels of output power and linearity while being easily integrated with surrounding circuitry, are a crucial component in wireless microwave systems. The book is divided into three parts, the first of which introduces readers to mm-wave wireless systems and power amplifiers. In turn, the second focuses on design principles and EDA concepts, while the third discusses future trends in power amplifier research. The book provides essential information on mm-wave power amplifier theory, as well as the implementation options and technologies involved in their effective design, equipping researchers, circuit designers and practicing engineers to design, model, analyze, test and implement high-performance, spectrally clean and energy-efficient mm-wave systems.
Author : Jefy Alex Jayamon
Publisher :
Page : 152 pages
File Size : 12,46 MB
Release : 2017
Category :
ISBN :
Emerging millimeter-wave applications, including high speed wireless communication using 5G standards, favor silicon technologies, both CMOS and SiGe, for transceiver design, due to the high level of integration at reduced cost and availability of high speed transistors. Efficient, linear and reliable high power amplifiers with broad bandwidth are needed at the transmitter front-ends to enable high data rate links at long distances. But the low breakdown voltage of CMOS FETs due to gate length scaling and other transistor non-idealities make the design of high power mm-wave amplifiers in deeply scaled CMOS nodes difficult. Circuit techniques like FET stacking provide a compact and efficient way of implementing high power mm-wave amplifiers reliably. Other power combining techniques such as on-chip and spatial power combining can be used along with FET stacking to achieve even higher output power levels. This thesis investigates the design of high power mm-wave power amplifiers at frequencies from 28 GHz to 94 GHz, using multiple power combining techniques. This work extends the use of FET stacking for high power PA design to 94 GHz. A 3-stack PA designed in 45 nm CMOS SOI with 17 dBm output power and 9% efficiency is presented. Using this PA as front-end, a CMOS PA-antenna array is designed, to additionally provide spatial power combining. The CMOS chip has a 2 x 4 array of pseudo-differential power amplifiers along with the signal distribution networks and pre-drivers. A quartz wafer with a 2 x 4 array of differential microstrip antennas deposited on it is placed on top of the CMOS chip, electromagnetically coupled to the PA outputs on the CMOS chip. The spatially power combined PA-antenna array achieved a measured equivalent isotropic radiated power (EIRP) of 33 dBm and an estimated output power of 24 dBm at 94 GHz. Modulated data measurements at 3 Gbps (375 MS/s, 256 QAM) speed using digital pre-distortion are demonstrated with the PA-antenna array. A novel layout style is introduced for stacked FET design at low mm-wave frequencies. A small multi-finger FET is laid out with fingers connected in series to create the stacked FET. The gate capacitors are realized around the FET with the back-end-of-line metal available in the CMOS process. Multiple multigate cells are interconnected to implement the stacked FET PA. A PA designed in this style in 45 nm CMOS SOI process achieved 24.8 dBm of output power and 29% PAE at 28 GHz with high reliability. This PA is very broadband and linear as shown by the modulated data measurements achieving a data rate of 36 Gbps (6 GS/s, 64 QAM) at 14 dBm with 9.3% PAE, with no digital predistortion. NFETs and PFETs available in nano-scale CMOS processes are compared and it is shown that in deeply scaled processes, PMOS devices are a viable alternative to NFETs due to their cut-off frequencies similar to those of NFETs, and higher breakdown voltages than NFETs. The first exclusively PMOS mm-wave PA design is reported. This 3-stack PA, made in 32 nm CMOS SOI process, achieved a maximum output power of 19.6 dBm and maximum efficiency of 24% at 78 GHz. All the designs reported in this thesis achieved either the highest output power or the highest PAE for a CMOS PA at their respective frequencies.
Author : Eric Kerhervé
Publisher : Elsevier
Page : 163 pages
File Size : 35,12 MB
Release : 2015-01-07
Category : Technology & Engineering
ISBN : 0124186815
This book provides an overview of current efficiency enhancement and linearization techniques for silicon power amplifier designs. It examines the latest state of the art technologies and design techniques to address challenges for RF cellular mobile, base stations, and RF and mmW WLAN applications. Coverage includes material on current silicon (CMOS, SiGe) RF and mmW power amplifier designs, focusing on advantages and disadvantages compared with traditional GaAs implementations. With this book you will learn: The principles of linearization and efficiency improvement techniques The architectures allowing the optimum design of multimode Si RF and mmW power amplifiers How to make designs more efficient by employing new design techniques such as linearization and efficiency improvement Layout considerations Examples of schematic, layout, simulation and measurement results Addresses the problems of high power generation, faithful construction of non-constant envelope constellations, and efficient and well control power radiation from integrated silicon chips Demonstrates how silicon technology can solve problems and trade-offs of power amplifier design, including price, size, complexity and efficiency Written and edited by the top contributors to the field
Author : Tak Shun Dickson Cheung
Publisher :
Page : 368 pages
File Size : 49,53 MB
Release : 2007
Category :
ISBN : 9780494394519
Wireless transmitters at mm-wave frequencies usually require costly III-V GaAs power amplifiers that must be packaged separately from mainstream silicon CMOS and BiCMOS circuits. This thesis studies the prospect of an integrable 3-stage power amplifier in a 100GHzfMAX 0.2microm SiGe HBT technology to facilitate cost-effective implementations of single-chip transceivers for 21--26GHz wireless applications. The amplifier utilizes an all common-base differential topology to maximize the power gain and extend the VCC supply to BVCEO of the transistors (1.8V). New on-chip components, such as interconnects with floating differential shields, self-shielding transformers and 4-way power combining/dividing baluns provide inter-stage coupling and single-ended interfaces at the input and output. On-chip ground isolation, low-inductance base interconnects and base ballast resistors are employed to ensure electrical and thermal stability. The current ratings of the on-chip passive components are designed to withstand the expected DC currents up to 110°C. The 2.45x2.45mm2 MMIC was mounted as a flip-chip and tested without a heatsink. It delivers 23dBm, 19.75% PAE at 22GHz, and 2ldBm, 13% PAE at 24GHz. The power gain is 19dB at a small-signal level and over 15dB at the maximum output power.
Author : Narek Rostomyan
Publisher :
Page : 140 pages
File Size : 18,77 MB
Release : 2018
Category :
ISBN :
Strong demand for mm-wave high data-rate links in emerging 5G communication systems has resulted in substantial interest in mm-wave silicon (Si) based radio front-ends. The efficiency of the PA is a significant factor in the overall power dissipation and thermal management of mm-wave transceivers which have arrays with a large number of antennas (RF channels). This dissertation focused mainly on circuit design techniques for cm/mm-wave CMOS power amplifier efficiency improvement at frequencies from 15 GHz to 28 GHz. In addition, a DSP based solution is proposed to increase efficiency and performance of cellular (LTE band) transmitters in the 1-3 GHz frequency range. For digital communication signals with multi-carrier modulation and high peak-to-average power ratios (PAPRs), high back-off efficiency of the PA is of significant importance. In the first part of the dissertation, possible implementations of linear and efficiency-enhanced CMOS PAs are described. The concept of stacking multiple FETs is applied in the design of symmetric and asymmetric Doherty power amplifiers, as well as compact linear PAs. The dissertation demonstrates that high power density can be achieved with PAs based on 4-stack power devices, while 2-stack devices can be designed to have exceptionally high efficiency due to lower losses. A two stage, high power Doherty PA that uses 4-stack devices in the final stages is demonstrated with more than 25 dBm output power and 25% back-off power added efficiency (PAE) at 6 dB back-off operating in the 15 GHz band. To minimize chip area, the Doherty combiner is based on an optimized, lumped element 90 degrees phase shifter. To overcome the inherent non-linear gain response of Doherty PAs and to minimize the complexity of digital pre-distortion (DPD) due to large channel bandwidth at mm-wave bands, a simple RF domain analog pre-distorter is demonstrated for the first time. Various compact, linear 2-stack PAs are demonstrated based nMOS and pMOS FETs for saturated output powers in the range of 20 dBm in the Ka-band. Performance and reliability advantages of pMOS based PAs are shown. Also, by using inter-node impedance tuning with a shunt feedback drain-source capacitor, the PAE of the 2-stack PAs is increased even further, resulting in world record 46% PAE for the pMOS PA at 26.5 GHz. Due to high passive losses in CMOS, achieving high efficiency Doherty PAs requires careful design and non-conventional synthesis methodology for the Doherty combiner. A high efficiency, symmetric Doherty PA for the Ka-band that is based on efficient 2-stack power devices and a low loss Doherty combiner synthesis technique is presented. At 6 dB back-off, the PAE exceeds 28% which corresponds to 1.4x higher PAE than achievable with ideal class B back-off from peak PAE. Such high efficiency is attained due to low combiner losses of 0.5 dB, which is less than half of what can be achieved with a conventional Doherty combiner. Furthermore, an asymmetric Doherty PA is reported that is based on low loss output Doherty combiner and uses a 2-stack cell in the main path and a 4-stack cell in the peaking path, thus improving efficiency at more than 6 dB back-off and achieving high output power. In addition, a compact modeling approach for large, parasitic-extracted PA transistors is presented, which considerably reduces simulation time and accelerates developments of CMOS PAs. A typical time-division duplex (TDD) transmit/receive (T/R) mm-wave front-end comprises a power amplifier, a low noise amplifier (LNA), an antenna switch, and appropriate passive matching and combining networks. In this thesis, a synthesis methodology is proposed that minimizes the overall losses by combining the PA output and the LNA input matching networks together with the T/R switch into one network. The technique improves mm-wave transceiver performance in terms of PA efficiency and LNA noise figure (NF). The proposed T/R combiner can achieve high linearity and can handle large PA output voltage swings. The architecture can be implemented in any process which provides high integration capability. A Ka-band implementation is demonstrated in CMOS SOI that includes a high power, 4-stack based PA and an inductively source degenerated, cascode based LNA. Within the front-end, the PA achieves saturated output power of 23.6 dBm with peak PAE of 28%, while the LNA achieves NF of 3.2 dB. Finally, in frequency division duplex (FDD) systems, spurious emissions from the transmitter (TX) can fall onto the receive (RX) band and lead to significant receiver desensitization. This dissertation proposes a DSP based solution that relies on a linear auxiliary receiver to cancel the RX band noise from the received signal. This technique allows reduction of duplexer rejection requirements in the RX band, and reduction of insertion loss in the TX band, thus, resulting in high PA efficiency and smaller duplexer footprint. PA architectures that inherently have high receive band noise (envelop tracking and digital PAs) can substantially benefit from this technique. More than 22 dB improvement in the signal to noise ratio (SNR) is shown without the presence of desired signal at the antenna.
Author : Gernot Hueber
Publisher : Cambridge University Press
Page : 455 pages
File Size : 18,78 MB
Release : 2019-06-20
Category : Technology & Engineering
ISBN : 1108757510
Discover the concepts, architectures, components, tools, and techniques needed to design millimeter-wave circuits for current and emerging wireless system applications. Focusing on applications in 5G, connectivity, radar, and more, leading experts in radio frequency integrated circuit (RFIC) design provide a comprehensive treatment of cutting-edge physical-layer technologies for radio frequency (RF) transceivers - specifically RF, analog, mixed-signal, and digital circuits and architectures. The full design chain is covered, from system design requirements through to building blocks, transceivers, and process technology. Gain insight into the key novelties of 5G through authoritative chapters on massive MIMO and phased arrays, and learn about the very latest technology developments, such as FinFET logic process technology for RF and millimeter-wave applications. This is an essential reading and an excellent reference for high-frequency circuit designers in both academia and industry.