[PDF] Low Power High Speed Adcs For Nanometer Cmos Integration eBook

Author : Zhiheng Cao
Publisher : Springer Science & Business Media
Page : 95 pages
File Size : 19,4 MB
Release : 2008-07-15
Category : Technology & Engineering
ISBN : 1402084501

GET BOOK

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested. 1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input. 2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash. 3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

Author : Weitao Li
Publisher : Springer
Page : 181 pages
File Size : 46,84 MB
Release : 2017-08-01
Category : Technology & Engineering
ISBN : 3319620126

GET BOOK

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won’t want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

Author : Mingzhen Wang
Publisher :
Page : 147 pages
File Size : 17,57 MB
Release : 2007
Category : Analog CMOS integrated circuits
ISBN :

GET BOOK

With higher-level integration driven by increasingly complex digital systems and downscaling CMOS processes available, system-on-a-chip (SoC) is an emerging technology of low power, high cost effectiveness and high reliability and is exceedingly attractive for applications in high-speed data conversion wireless and wideband communication systems. This research presents a novel ADC comparator design methodology; the speed and performance of which is not restricted by the supply voltage reduction and device linearity deterioration in scaling-down CMOS processes. By developing a dynamic offset suppression technique and a circuit optimization method, the comparator can achieve a 3 dB frequency of 2 GHz in 130 nanometer (nm) CMOS process. Combining this new comparator design and a proposed pipelined thermometer-Gray- binary encoder designed by the DCVSPG logic, a high-speed, low-voltage clocked-digital- comparator (CDC) pipelined CMOS flash ADC architecture is proposed for wideband communication SoC. This architecture has advantages of small silicon area, low power, and low cost. Three CDC-based pipelined CMOS flash ADCs were implemented in 130 nm CMOS process and their experimental results are reported: 1. 4-b, 2.5-GSPS ADC: SFDR of 21.48-dB, SNDR of 15.99-dB, ENOB of 2.4-b, ERBW of 1-GHz, power of 7.9-mW, and area of 0.022-mm2. 2. 4-b, 4-GSPS ADC: SFDR of 25-dB, SNDR of 18.6-dB, ENOB of 2.8-b, ERBW of 2-GHz, power of 11-mW. 3. 6-b, 4-GSPS ADC: SFDR of 48-dB at a signal frequency of 11.72-MHz, SNDR of 34.43-dB, ENOB of 5.4-b, power of 28-mW. An application of the proposed CDC-based pipelined CMOS flash ADC is 1-GHz bandwidth, 2.5-GSPS digital receiver on a chip. To verify the performance of the receiver, a mixed-signal block-level simulation and verification flow was built in Cadence AMS integrated platform. The verification results of the digital receiver using a 4-b 2.5-GSPS CDC-based pipelined CMOS ADC, a 256-point, 12-point kernel function FFT and a frequency detection logic show that two tone signals up to 1125 MHz can be detected and discriminated. A notable contribution of this research is that the proposed ADC architecture and the comparator design with dynamic offset suppression and optimization are extremely suitable for future VDSM CMOS processes and make “all-digital” receiver SoC design practical.

Author : Bert Lenaerts
Publisher : Springer Science & Business Media
Page : 230 pages
File Size : 10,89 MB
Release : 2008-10-14
Category : Technology & Engineering
ISBN : 1402090757

GET BOOK

Omnidirectional Inductive Powering for Biomedical Implants investigates the feasibility of inductive powering for capsule endoscopy and freely moving systems in general. The main challenge is the random position and orientation of the power receiving system with respect to the emitting magnetic field. Where classic inductive powering assumes a predictable or fixed alignment of the respective coils, the remote system is now free to adopt just any orientation while still maintaining full power capabilities. Before elaborating on different approaches towards omnidirectional powering, the design and optimisation of a general inductive power link is discussed in all its aspects. Special attention is paid to the interaction of the inductive power link with the patient’s body. Putting theory into practice, the implementation of an inductive power link for a capsule endoscope is included in a separate chapter.

Author : Yefim Poberezhskiy
Publisher : Artech House
Page : 340 pages
File Size : 44,43 MB
Release : 2018-12-31
Category : Technology & Engineering
ISBN : 1630814016

GET BOOK

This comprehensive resource provides the latest information on digitization and reconstruction (D&R) of analog signals in digital radios. Readers learn how to conduct comprehensive analysis, concisely describe the major signal processing procedures carried out in the radios, and demonstrate the dependence of these procedures on the quality of D&R. The book presents and analyzes the most promising and theoretically sound ways to improve the characteristics of D&R circuits and illustrate the influence of these improvements on the capabilities of digital radios. The book is intended to bridge the gap that exists between theorists and practical engineers developing D&R techniques by introducing new signal transmission and reception methods that can effectively utilize the unique capabilities offered by novel digitization and reconstruction techniques.

Author : Muhammed Bolatkale
Publisher : Springer
Page : 135 pages
File Size : 20,96 MB
Release : 2014-05-27
Category : Technology & Engineering
ISBN : 3319058401

GET BOOK

This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nano meter-CMOS processes. The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators. Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.

Author : Refet Firat Yazicioglu
Publisher : Springer Science & Business Media
Page : 172 pages
File Size : 41,99 MB
Release : 2008-10-16
Category : Technology & Engineering
ISBN : 1402090935

GET BOOK

Biopotential Readout Circuits for Portable Acquisition Systems describes one of the main building blocks of such miniaturized biomedical signal acquisition systems. The focus of this book is on the implementation of low-power and high-performance integrated circuit building blocks that can be used to extract biopotential signals from conventional biopotential electrodes. New instrumentation amplifier architectures are introduced and their design is described in detail. These amplifiers are used to implement complete acquisition demonstrator systems that are a stepping stone towards practical miniaturized and low-power systems.

Author : Andrea Baschirotto
Publisher : Springer Nature
Page : 324 pages
File Size : 13,53 MB
Release : 2019-10-24
Category : Technology & Engineering
ISBN : 3030252671

GET BOOK

This book is based on the 18 tutorials presented during the 28th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including next-generation analog-to-digital converters , high-performance power management systems and technology considerations for advanced IC design. For anyone involved in analog circuit research and development, this book will be a valuable summary of the state-of-the-art in these areas. Provides a summary of the state-of-the-art in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of next-generation analog-to-digital converters, high-performance power management systems, and technology considerations for advanced IC design.

Author : Vazgen Melikyan
Publisher : Springer Nature
Page : 351 pages
File Size : 33,29 MB
Release : 2024-01-31
Category : Technology & Engineering
ISBN : 3031507142

GET BOOK

This book describes machine learning-based new principles, methods of design and optimization of high-speed integrated circuits, included in one electronic system, which can exchange information between each other up to 128/256/512 Gbps speed. The efficiency of methods has been proven and is described on the examples of practical designs. This will enable readers to use them in similar electronic system designs. The author demonstrates newly developed principles and methods to accelerate communication between ICs, working in non-standard operating conditions, considering signal deviation compensation with linearity self-calibration. The observed circuit types also include but are not limited to mixed-signal, high performance heterogeneous integrated circuits as well as digital cores.

Author : Mostafa Haroun
Publisher :
Page : pages
File Size : 47,18 MB
Release : 2014
Category :
ISBN :

GET BOOK

"The use of high-speed high-resolution analog-to-digital converters (ADCs) allows part of the signal processing to be done in the digital domain allowing for higher system integration and cheaper fabrication. Becoming more in use, hand-held devices have low-power requirements to allow for longer battery life. Also, designing ADCs in nanometer digital CMOS technologies make them more integrable with digital processing blocks and cheaper. This thesis aims at designing a high-speed (16MS/s conversion rate) high-resolution (12bits) Delta-Sigma modulator with low-power consumption in nanometer CMOS. Delta-Sigma modulators can achieve high resolution in low and medium speed applications. For higher speed applications, the oversampling ratio (OSR) will have to be kept low to avoid inefficient design. However, lowering the OSR requires special care in the design starting from the architecture until the full circuit implementation. In nanometer CMOS technologies, analog properties, such as intrinsic gain, degrade which might result in a higher power consumption. Moreover, the low nominal supply voltages associated with such technologies adds more challenges to the design of a low distortion power-efficient Delta-Sigma modulator. Targeting a specic resolution, lowering the voltage supply usually results in a higher power consumption. This thesis suggests possible solutions to achieve low power consumption while targeting high-speed applications in nanometer low-voltage-supply environment.This thesis presents a low-power Discrete-Time (DT) Delta-Sigma modulator making use of a single-loop multibit DT digital input-feedforward Delta-Sigma architecture. The main feature of this architecture is the reduced signal swings at the output of the integrators which allows the use of a low voltage supply. The low-power Switched-Capacitor (SC) implementation is ensured by using a novel opamp switching technique, optimizing simultaneous opamp's settling in cascaded nondelaying SC integrators, and using non-overlapping clock phases with unequal duty-cycles. The novel opamp switching technique is based on a current-mirror opamp with switchable transconductances. The current-mirror opamp works with full current during the charge-transfer phase while the output current is partially switched off during the sampling phase. Power saving can be achieved while ensuring that the opamp output is available during both phases. The simultaneous settling of series opamps in a two cascaded nondelaying SC integrators scheme is looked at as a two-pole system where power optimization is necessary to ensure minimum power consumption while meeting the settling requirements. The use of clock phases with unequal duty-cycles gives the designer an extra degree of freedom to further power optimize the design. The experimental Delta-Sigma ADC is a 4th-order 5.5bits single-loop Delta-Sigma modulator with an OSR of 8. The design starts with the structural-level aspects in which system-level decisions are made and simulations are carried-out with behavioral models to find the suitable circuit parameters. Circuit-level design in then considered to design each block and simulate the full-system. Fabricated in 1V 65nm CMOS, the Delta-Sigma modulator prototype occupies an active area of 1.2mm2. Although the targeted resolution is about 12bits, the experimental results shows a dynamic range (DR) of 66dB (11bits) over an 8MHz bandwidth while consuming 26mW and a peak SNR/SNDR of 64/58.5dB. The proposed opamp switching technique brings the total power consumption from 29mW to 26mW without affecting the performance (SNDR stays at 58.5dB). The deviation in experimental performance, from simulations, in thought to be due to higher parasitic capacitance requiring higher bias currents which results in drop of opamp dc gain. Compared to state of the art high-speed high-resolution Delta-Sigma modulators operated from 1V supply and fabricated in CMOS, it achieves a reasonable Figure-of-Merit." --