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Examines all important aspects of integrated circuit design, fabrication, assembly and test processes as they relate to quality and reliability. This second edition discusses in detail: the latest circuit design technology trends; the sources of error in wafer fabrication and assembly; avenues of contamination; new IC packaging methods; new in-line process monitors and test structures; and more.;This work should be useful to electrical and electronics, quality and reliability, and industrial engineers; computer scientists; integrated circuit manufacturers; and upper-level undergraduate, graduate and continuing-education students in these disciplines.
Examines all important aspects of integrated circuit design, fabrication, assembly and test processes as they relate to quality and reliability. This second edition discusses in detail: the latest circuit design technology trends; the sources of error in wafer fabrication and assembly; avenues of contamination; new IC packaging methods; new in-line process monitors and test structures; and more.;This work should be useful to electrical and electronics, quality and reliability, and industrial engineers; computer scientists; integrated circuit manufacturers; and upper-level undergraduate, graduate and continuing-education students in these disciplines.
This is a program directed to establish techniques for the control of integrated circuit quality and reliability. The primary objective of this program was to investigate a method to monitor integrated circuit fabrication which would provide information about the quality and reliability of the device. The use of the test pattern concept, TEG, for in-process quality control and device reliability of integrated circuits was investigated during the fabrication and reliability testing phases of integrated circuit production. The Test Element Group (TEG), which was diffused on the wafer at the same time as the elements of the integrated circuit, proved to be a very successful vehicle for achieving the goals of this program. The TEG was made up of a number of selected elements in the integrated circuit diffusion pattern, metallized and connected for test evaluation as discrete components. The relationship was investigated between in-process variables of semiconductor fabrication, pre-stress characteristics of TEGS and integrated circuits and the post-stress characteristics of TEGS and integrated circuits.
Funktionstests an integrierten Schaltungen sind für deren Zuverlässigkeit von herausragender Bedeutung. Erstmals werden in diesem Werk die speziellen Präparationstechniken für die Fehleranalyse beschrieben. Ausgehend von den theoretischen Grundlagen erläutert der Autor in praxisnahem Stil die verschiedenen Techniken, die das Zurückverfolgen von Ausfällen ermöglichen.
The use of the test pattern concept, TEG, for in-process quality control and device reliability of integrated circuits was investigated during the fabrication and reliability testing phases of integrated circuit production. The Test Element Group (TEG), which was diffused on the wafer at the same time as the elements of the integrated circuit, proved to be a very successful vehicle for achieving the goals of this program. The TEG was made up of a number of selected elements in the integrated circuit diffusion pattern, metallized and connected for test evaluation as discrete components. The relationship was investigated between in-process variables of semi-conductor fabrication, pre-stress characteristics of TEGS and integrated circuits and the post-stress characteristics of TEGS and integrated circuits. The basic purpose of this program has been met.
In Thermal and Power Management of Integrated Circuits, power and thermal management issues in integrated circuits during normal operating conditions and stress operating conditions are addressed. Thermal management in VLSI circuits is becoming an integral part of the design, test, and manufacturing. Proper thermal management is the key to achieve high performance, quality and reliability. Performance and reliability of integrated circuits are strong functions of the junction temperature. A small increase in junction temperature may result in significant reduction in the device lifetime. This book reviews the significance of the junction temperature as a reliability measure under nominal and burn-in conditions. The latest research in the area of electro-thermal modeling of integrated circuits will also be presented. Recent models and associated CAD tools are covered and various techniques at the circuit and system levels are reviewed. Subsequently, the authors provide an insight into the concept of thermal runaway and how it may best be avoided. A section on low temperature operation of integrated circuits concludes the book.
Circuit designers, packaging engineers, printed board fabricators, and procurement personnel will find this book's microelectronic package design-for-reliability guidelines and approaches essential for achieving their life-cycle, cost-effectiveness, and on-time delivery goals. Its uniquely organized, time-phased approach to design, development, qualification, manufacture, and in-service management shows you step-by-step how to: * Define realistic system requirements in terms of mission profile, operating life, performance expectations, size, weight, and cost * Define the system usage environment so that all operating, shipping, and storage conditions, including electrical, thermal, radiation, and mechanical loads, are assessed using realistic data * Identify potential failure modes, sites, mechanisms, and architecture-stress interactions--PLUS appropriate measures you can take to reduce, eliminate, or accommodate expected failures * Characterize materials and processes by the key controllable factors, such as types and levels of defects, variations in material properties and dimensions, and the manufacturing and assembly processes involved * Use experiment, step-stress, and accelerated methods to ensure optimum design before production begins Detailed design guidelines for substrate...wire and wire, tape automated, and flip-chip bonding...element attachment and case, lead, lead and lid seals--incorporating dimensional and geometric configurations of package elements, manufacturing and assembly conditions, materials selection, and loading conditions--round out this guide's comprehensive coverage. Detailed guidelines for substrate...wire and wire, tape automated, and flip-chip bonding...element attachment and case, lead, lead and lid seals--incorporating dimensional and geometric configurations of package elements, manufacturing and assembly conditions, materials selection, and loading conditions--round out this guide's comprehensive coverage. of related interest... PHYSICAL ARCHITECTURE OF VLSI SYSTEMS --Allan D. Kraus, Robert Hannemann and Michael Pecht For the professional engineer involved in the design and manufacture of products containing electronic components, here is a comprehensive handbook to the theory and methods surrounding the assembly of microelectronic and electronic components. The book focuses on computers and consumer electronic products with internal subsystems that reflect mechanical design constraints, cost limitations, and aesthetic and ergonomic concerns. Taking a total system approach to packaging, the book systematically examines: basic chip and computer architecture; design and layout; interassembly and interconnections; cooling scheme; materials selection, including ceramics, glasses, and metals; stress, vibration, and acoustics; and manufacturing and assembly technology. 1994 (0-471-53299-1) pp. SOLDERING PROCESSES AND EQUIPMENT --Michael G. Pecht This comprehensive, fundamentals first handbook outlines the soldering methods and techniques used in the manufacture of microelectronic chips and electronic circuit boards. In a clear, easy-to-access format, the book discusses: soldering processes and classification; the material dynamics of heat soldering when assembling differing materials; wave and reflow soldering; controlling contamination during manufacturing cleanings; techniques for assuring reliability and quality control during manufacturing; rework, repair, and manual assembly; the modern assembly / repair station; and more. The book also provides clear guidelines on assembly techniques as well as an appendix of various solder equipment manufacturers. 1993 (0-471-59167-X) 312 pp.
The report describes results of a study aimed at lowering the cost of high-reliability integrated circuits. The circuit family chosen for the study was RCA's CMOS product line, and recommendations are developed specifying changes in the existing process line, aimed at improving the reliability of the finished products. The intention has been to provide reliability inspection and quality control procedures which can be distributed throughout the manufacturing process, replacing the present approach of performing all high-reliability screening at the end of the manufacturing process. The cost and trade-offs of implementing these changes have been analyzed where possible. Where such analysis was not possible, a research schedule was prepared to provide the data necessary for evaluation of the proposed change. The most important of the proposed changes form an integrated concept in which wafers move through an automated production line under computer control.
Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them. This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future? Chapters discuss: failure sites, operational loads, and failure mechanism intrinsic device sensitivities electromigration hot carrier aging time dependent dielectric breakdown mechanical stress induced migration alpha particle sensitivity electrostatic discharge (ESD) and electrical overstress latch-up qualification screening guidelines for designing reliability Guidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.
An evaluation was accomplished of the design, fabrication, inspection and testing of integrated circuits (ICs) as practiced by the electronics industry. An analysis was made of failure modes and causes of failure. The purpose was to disseminate information on current IC technology to AFSC Quality Assurance personnel. A corollary purpose was to improve the quality and reliability of hardware using these devices. (Author).