[PDF] Inductors In High Performance Silicon Radio Frequency Integrated Circuits eBook

Author : Richard D. Lutz
Publisher :
Page : 310 pages
File Size : 38,73 MB
Release : 2005
Category : Electric inductors
ISBN :

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Spiral inductors are a key component of mixed-signal and analog integrated circuits (IC's). Such circuits are often fabricated using silicon-based technology, owing to the inherent low-cost and high volume production aspects. However, semiconducting substrate materials such as silicon can have adverse effects on spiral inductor performance due to the lossy nature of the material. Since the operating requirements of many high performance IC's demand reactive components that have high Quality Factor's (Q's), and are thus low loss devices, the need for accurate modeling of such structures over lossy substrate media is key to successful circuit design. The Q's of commonly available off-chip inductors are in the range of 50- 100 for frequencies ranging up to a few gigahertz. Since off-chip inductors must be connected through package pins, solder bumps, etc., which all contribute additional loss and thus lower the apparent Q of an external device, the typical on-chip Q requirement for a given RFIC design is generally lower than that for an off-chip spiral solution. However, a spiral inductor that was designed and fabricated originally in a low loss technology such as thin-film alumina may have substantially worse performance in regard to Q if it is used in a silicon-based technology, owing to the conductive substrate. For this reason, it is imperative that semiconducting substrate effects be accurately accounted for by any modeling effort for monolithic spirals in RFICs. This thesis presents a complete modeling solution for both single and multi-level spiral inductors over lossy silicon substrates, along with design considerations and methods for mitigation of the undesirable performance effects of semiconducting substrates. The modeling solution is based on Spectral Domain Approach (SDA) solutions for frequency dependent complex capacitive (i.e. both capacitance and conductance) parasitic elements combined with a quasi-magnetostatic field solution for calculation of the frequency dependent complex inductive (i.e. both inductance and resistance) terms. The effects of geometry and process variations are considered as well as the incorporation of Patterned Ground Shields (PGS) for the purpose of Q enhancement. Proposals for future extensions of this work are discussed in the concluding chapter.

Author : Mina Danesh
Publisher :
Page : 0 pages
File Size : 26,92 MB
Release : 1999
Category :
ISBN :

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A novel parameter extraction technique is applied to the modeling of rectangular spiral inductors and validated with measurements and simulations. To enhance the inductor quality ('Q') factor, a differentially excited symmetric inductor is used. Compared with a single-ended configuration, the differential structure offers a higher 'Q'-factor over a wider range of frequencies. Application of the symmetric inductor model is demonstrated using two oscillator designs in which a differentially excited symmetric inductor is compared with conventional spiral inductors. The symmetric inductor improves the overall circuit performance and saves chip area.

Author : Ali M. Niknejad
Publisher : Springer Science & Business Media
Page : 193 pages
File Size : 28,7 MB
Release : 2005-12-15
Category : Technology & Engineering
ISBN : 0306470381

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The modern wireless communication industry has put great demands on circuit designers for smaller, cheaper transceivers in the gigahertz frequency range. One tool which has assisted designers in satisfying these requirements is the use of on-chip inductiveelements (inductors and transformers) in silicon (Si) radio-frequency (RF) integrated circuits (ICs). These elements allow greatly improved levels of performance in Si monolithic low-noise amplifiers, power amplifiers, up-conversion and down-conversion mixers and local oscillators. Inductors can be used to improve the intermodulation distortion performance and noise figure of small-signal amplifiers and mixers. In addition, the gain of amplifier stages can be enhanced and the realization of low-cost on-chip local oscillators with good phase noise characteristics is made feasible. In order to reap these benefits, it is essential that the IC designer be able to predict and optimize the characteristics of on-chip inductiveelements. Accurate knowledge of inductance values, quality factor (Q) and the influence of ad- cent elements (on-chip proximity effects) and substrate losses is essential. In this book the analysis, modeling and application of on-chip inductive elements is considered. Using analyses based on Maxwells equations, an accurate and efficient technique is developed to model these elements over a wide frequency range. Energy loss to the conductive substrate is modeled through several mechanisms, including electrically induced displacement and conductive c- rents and by magnetically induced eddy currents. These techniques have been compiled in a user-friendly software tool ASITIC (Analysis and Simulation of Inductors and Transformers for Integrated Circuits).

Author : Genemala Haobijam
Publisher : Springer Science & Business Media
Page : 116 pages
File Size : 37,62 MB
Release : 2013-09-07
Category : Technology & Engineering
ISBN : 813221515X

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The book addresses the critical challenges faced by the ever-expanding wireless communication market and the increasing frequency of operation due to continuous innovation of high performance integrated passive devices. The challenges like low quality factor, design complexity, manufacturability, processing cost, etc., are studied with examples and specifics. Silicon on-chip inductor was first reported in 1990 by Nguyen and Meyer in a 0.8 μm silicon bipolar complementary metal oxide semiconductor technology (BiCMOS). Since then, there has been an enormous progress in the research on the performance trends, design and optimization, modeling, quality factor enhancement techniques, etc., of spiral inductors and significant results are reported in literature for various applications. This book introduces an efficient method of determining the optimized layout of on chip spiral inductor. The important fundamental tradeoffs of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is also explored. The authors proposed an algorithm for accurate design and optimization of spiral inductors using a 3D electromagnetic simulator with minimum number of inductor structure simulations and thereby reducing its long computation time. A new multilayer pyramidal symmetric inductor structure is also proposed in this book. Being multilevel, the proposed inductor achieves high inductance to area ratio and hence occupies smaller silicon area.

Author : Jaime Aguilera
Publisher : Springer Science & Business Media
Page : 203 pages
File Size : 16,34 MB
Release : 2007-05-08
Category : Technology & Engineering
ISBN : 0306487055

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Intended for engineers who are starting out in the design of integrated inductors, this book describes the whole design flow, basic selection of the geometry and optimisation of the quality by redesigning the geometry, measurement and de-embedding and characterisation.

Author :
Publisher :
Page : 8 pages
File Size : 25,80 MB
Release : 1998
Category :
ISBN :

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Strong demand for wireless communication devices has motivated research directed toward monolithic integration of transceivers. The fundamental electronic component least compatible with silicon integrated circuits is the inductor, although a number of inductors are required to implement oscillators, filters and matching networks in cellular devices. Spiral inductors have been integrated into the silicon IC metallization sequence but have not performed adequately due to coupling to the silicon which results in parasitic capacitance and loss. We have, for the first time, fabricated three dimensional coil inductors on silicon which have significantly lower capacitive coupling and loss and which now exceed the requirements of potential applications. Quality factors of 30 at 1 GHz have been measured in single turn devices and Q> 16 in 2 and 4 turn devices. The reduced Q for multiturn devices appears to be related to eddy currents in outer turns generated by magnetic fields from current in neighboring turns. Higher Q values significantly in excess of 30 are anticipated using modified coil designs.

Author : Ao Zhang
Publisher : World Scientific
Page : 322 pages
File Size : 15,77 MB
Release : 2023-03-21
Category : Technology & Engineering
ISBN : 9811255377

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This comprehensive compendium describes the basic modeling techniques for silicon-based semiconductor devices, introduces the basic concepts of silicon-based passive and active devices, and provides its state-of-the-art modeling and equivalent circuit parameter extraction methods.The unique reference text benefits practicing engineers, technicians, senior undergraduate and first-year graduate students working in the areas of RF, microwave and solid-state device, and integrated circuit design.

Author : Yehea I. Ismail
Publisher : Springer Science & Business Media
Page : 310 pages
File Size : 24,75 MB
Release : 2012-12-06
Category : Technology & Engineering
ISBN : 1461516854

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The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies. On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively. On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance. emOn-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.