[PDF] Error Detection Of Arithmetic And Logical Operations In A Processor Using Low Cost Residue Codes eBook

Author : National Aeronautics and Space Administration (NASA)
Publisher : Createspace Independent Publishing Platform
Page : 28 pages
File Size : 38,22 MB
Release : 2018-07-25
Category :
ISBN : 9781724269430

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A method of concurrent error detection for arithmetic processors is described. Low-cost residue codes with check-length l and checkbase m = 2 to the l power - 1 are described for checking arithmetic operations of addition, subtraction, multiplication, division complement, shift, and rotate. Of the three number representations, the signed-magnitude representation is preferred for residue checking. Two methods of residue generation are described: the standard method of using modulo m adders and the method of using a self-testing residue tree. A simple single-bit parity-check code is described for checking the logical operations of XOR, OR, and AND, and also the arithmetic operations of complement, shift, and rotate. For checking complement, shift, and rotate, the single-bit parity-check code is simpler to implement than the residue codes. Lim, R. S. Ames Research Center NASA-TP-1528, A-7810 RTOP 366-18-50-00-00

Author : Michael Brendan Sullivan
Publisher :
Page : 78 pages
File Size : 49,26 MB
Release : 2010
Category :
ISBN :

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Residue codes have successfully been used for decades as a low overhead method of arithmetic error detection. This work explores the design space of residue checking for error detection in processors with modern word sizes and technology nodes. The area overheads of detecting arithmetic errors are considered for a variety of processor configurations, ranging from those best suited for embedded processors to those best for high-performance computers. The ultimate goal of this work is to enable the study of low overhead arithmetic error protection and correction in a wider variety of computer architectures than has previously been attempted in a systematic manner.

Author : Stanford University Stanford Electronics Laboratories. Digital Systems Laboratory
Publisher :
Page : 72 pages
File Size : 15,62 MB
Release : 1975
Category :
ISBN :

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A self-checking processor has redundant hardware to insure that no likely failure can cause undetected errors and all likely failures are detected in normal operation. We show how error-detecting codes and self-checking circuits can be used to achieve these properties in a microprogrammed processor. The choice of error-detecting codes and the placement of checkers to monitor coded data paths are discussed. The use of codes to detect errors in arithmetic and logic operations and microprogram control units is described. An example processor design is given and some observations on the diagnosis and repair of such a processor are made. From the example design it appears that somewhat less than 50% overall redundancy is required to guarantee the detection of all failures that affect a single medium- or large-scale integration circuit package.