[PDF] Domain Specific Computing In Tightly Coupled Heterogeneous Systems eBook

Author : Anthony Michael Cabrera
Publisher :
Page : 0 pages
File Size : 21,90 MB
Release : 2020
Category :
ISBN :

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Over the past several decades, researchers and programmers across many disciplines have relied on Moores law and Dennard scaling for increases in compute capability in modern processors. However, recent data suggest that the number of transistors per square inch on integrated circuits is losing pace with Moores laws projection due to the breakdown of Dennard scaling at smaller semiconductor process nodes. This has signaled the beginning of a new "golden age in computer architecture" in which the paradigm will be shifted from improving traditional processor performance for general tasks to architecting hardware that executes a class of applications in a high-performing manner. This shift will be paved, in part, by making compute systems more heterogeneous and investigating domain specific architectures. However, the notion of domain specific architectures raises many research questions. Specifically, what constitutes a domain? How does one architect hardware for a specific domain? In this dissertation, we present our work towards domain specific computing. We start by constructing a guiding definition for our target domain and then creating a benchmark suite of applications based on our domain definition. We then use quantitative metrics from the literature to characterize our domain in order to gain insights regarding what would be most beneficial in hardware targeted specifically for the domain. From the characterization, we learn that data movement is a particularly salient aspect of our domain. Motivated by this fact, we evaluate our target platform, the Intel HARPv2 CPU+FPGA system, for architecting domain specific hardware through a portability and performance evaluation. To guide the creation of domain specific hardware for this platform, we create a novel tool to quantify spatial and temporal locality. We apply this tool to our benchmark suite and use the generated outputs as features to an unsupervised clustering algorithm. We posit that the resulting clusters represent sub-domains within our originally specified domain; specifically, these clusters inform whether a kernel of computation should be designed as a widely vectorized or deeply pipelined compute unit. Using the lessons learned from the domain characterization and hardware platform evaluation, we outline our process of designing hardware for our domain, and empirically verify that our prediction regarding a wide or deep kernel implementation is correct.

Author : Wim Vanderbauwhede
Publisher : Springer Science & Business Media
Page : 798 pages
File Size : 17,18 MB
Release : 2013-08-23
Category : Technology & Engineering
ISBN : 1461417910

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High-Performance Computing using FPGA covers the area of high performance reconfigurable computing (HPRC). This book provides an overview of architectures, tools and applications for High-Performance Reconfigurable Computing (HPRC). FPGAs offer very high I/O bandwidth and fine-grained, custom and flexible parallelism and with the ever-increasing computational needs coupled with the frequency/power wall, the increasing maturity and capabilities of FPGAs, and the advent of multicore processors which has caused the acceptance of parallel computational models. The Part on architectures will introduce different FPGA-based HPC platforms: attached co-processor HPRC architectures such as the CHREC’s Novo-G and EPCC’s Maxwell systems; tightly coupled HRPC architectures, e.g. the Convey hybrid-core computer; reconfigurably networked HPRC architectures, e.g. the QPACE system, and standalone HPRC architectures such as EPFL’s CONFETTI system. The Part on Tools will focus on high-level programming approaches for HPRC, with chapters on C-to-Gate tools (such as Impulse-C, AutoESL, Handel-C, MORA-C++); Graphical tools (MATLAB-Simulink, NI LabVIEW); Domain-specific languages, languages for heterogeneous computing(for example OpenCL, Microsoft’s Kiwi and Alchemy projects). The part on Applications will present case from several application domains where HPRC has been used successfully, such as Bioinformatics and Computational Biology; Financial Computing; Stencil computations; Information retrieval; Lattice QCD; Astrophysics simulations; Weather and climate modeling.

Author : Hui Huang
Publisher :
Page : 116 pages
File Size : 12,95 MB
Release : 2014
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ISBN :

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It is known that with the support of domain-specific customizable heterogeneous architecture, energy efficiency can be significantly improved by adapting architectures to match the requirements of a given application or application domain. One of the main challenges in this emerging trend is how to efficiently take the advantage of the heterogeneity and customization features in those architectures. This research investigates developing efficient compiler support to automate the platform mapping and code transformation process. First, considering customizable computing engines, we have investigated both tightly-coupled and loosely-coupled computing elements. In terms of tightly-coupled computing engine customization, customizable vector ISA supports are explored to better exploit data-level parallelism in the high performance applications. We identify the needs and opportunities to explore customized vector instructions and quantify their benefits. We build an automatic compilation flow in LLVM-2.7 compiler infrastructure to efficiently identify customized vector instructions from a given set of applications. The memory alignment overhead, which is known to be critical for vector processing efficiency, has been optimized in our customized vector ISA identification flow. To support efficient vector ISA customization, we design a composable vector unit (CVU), which can be used both separately and in a chained mode, to support a large number of virtualized custom vector instructions with minimal area overhead. The results show that our approach achieves an average 27% speedup over the state-of-art vector ISA. Second, in terms of loosely-coupled computing elements, it is known that on-chip accelerators are combined with general-purpose cores in an effort to amortize the cost of the design across many application domains. In recent days programmable accelerators (PA) are widely investigated in the design of domain-specific architectures to improve the system performance and power. Micro-architectures with a series of PAs have been explored to provide more general supports for customization. One important feature in the PA-rich systems is that the target computational kernels are compiled with a set of pre-defined PA templates and dynamically mapped to real PAs at runtime. This imposes a demanding challenge on the compiler side regarding how to generate high-quality PA mapping code. We present an efficient PA compilation flow, which is fairly scalable in mapping large computation kernels into PA-rich architectures and provides support for full pipelined execution to achieve the highest energy efficiency. A concept called maximal PA candidate is proposed to drastically reduce the number of input PA candidates in the mapping phase without influencing the overall mapping optimality. Efficient pre & ndash;selection and pruning techniques are employed to further speedup the maximal PA mapping process. Our experimental results show that for 12 computation-intensive standard benchmarks, the proposed approach achieves a significant improvement on the compilation time comparing to the state-of-art PA compilation approaches. The average mapping quality is improved by 23.8% and 32.5% for connected PA candidates and disjoint ones, respectively. Third, in domain & ndash;specific computing multi & ndash;level software & ndash;controlled memories have been commonly used to better utilize domain & ndash;specific knowledge of particular applications and achieve high performance/energy efficiency. At the level of L1 memory, while conventional cache works well for general workloads, some recent works explore the idea of using a hybrid cache, which can be flexibly partitioned into a traditional cache and an SCM. In the hybrid cache architecture, first & ndash;level SCM has been utilized as prefetch buffer to hide memory access latency. We quantify the impact of data reuse on SCM prefetching efficiency and propose a reuse & ndash;aware SCM prefetching (RASP) scheme, which shows 31.2% performance gain over previous work. On the other hand, SCM has also been widely used in last level on & ndash;board memory to reduce the data movements between computing cores (i.e. host processor and accelerator cores), which is usually transferred through low & ndash;bandwidth bus and known to be one of the major performance bottlenecks in modern heterogeneous systems. To efficiently manage LL & ndash;SCM, we propose a task & ndash;level & ndash;reuse & ndash;graph (TLRM) based LL & ndash;SCM data movement scheme to minimize the amount of data transfers between heterogeneous computing cores through the slow PCIe bus. With the introduction of TLRM, the data movement optimization between host and accelerator cores can be approximated using a linear programming based solution, and an average 25% reduction of host & ndash;accelerator data transfers is observed from previous work.

Author : Fernando Rincón
Publisher : Springer Nature
Page : 408 pages
File Size : 33,90 MB
Release : 2020-03-25
Category : Computers
ISBN : 3030445348

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This book constitutes the proceedings of the 16th International Symposium on Applied Reconfigurable Computing, ARC 2020, held in Toledo, Spain, in April 2020. The 18 full papers and 11 poster presentations presented in this volume were carefully reviewed and selected from 40 submissions. The papers are organized in the following topical sections: design methods & tools; design space exploration & estimation techniques; high-level synthesis; architectures; applications.

Author : Nobuhiko Koike
Publisher : SIAM
Page : 184 pages
File Size : 43,18 MB
Release : 2000-01-01
Category : Computers
ISBN : 9780898714494

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This symposium brought together technology providers, application program developers, and industrial users of high performance computing systems. The articles address the current and future developments of computing systems for numerical simulation seen from these various viewpoints. The main issues raised include these questions:

Author : VAHID LARI
Publisher : Springer
Page : 165 pages
File Size : 12,19 MB
Release : 2016-07-08
Category : Technology & Engineering
ISBN : 9811010587

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This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

Author : Athman Bouguettaya
Publisher : Springer Science & Business Media
Page : 229 pages
File Size : 27,22 MB
Release : 2012-12-06
Category : Business & Economics
ISBN : 1461555671

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Information systems are the backbone of many of today's computerized applications. Distributed databases and the infrastructure needed to support them have been well studied. However, this book is the first to address distributed database interoperability by examining the successes and failures, various approaches, infrastructures, and trends of the field. A gap exists in the way that these systems have been investigated by real practitioners. This gap is more pronounced than usual, partly because of the way businesses operate, the systems they have, and the difficulties created by systems' autonomy and heterogeneity. Telecommunications firms, for example, must deal with an increased demand for automation while at the same time continuing to function at their current level. While academics are focusing on investigating differences between distributed databases, federated databases, heterogeneous databases, and, more generally, among loosely connected and tightly coupled systems, those who have to deal with real problems right away know that the only relevant research is the one that will ensure that their system works to produce reasonably correct results. Interconnecting Heterogeneous Information Systems covers the underlying principles and infrastructures needed to realize truly global information systems. The book discusses technologies related to middleware, the Web, workflows, transactions, and data warehousing. It also overviews architectures with a discussion of critical issues. The book gives an overview of systems that can be viewed as learning platforms. While these systems do not translate to successful commercial realities, they push the envelope in terms of research. Successful commercial systems have benefited from the experiments conducted in these prototypes. The book includes two case studies based on the authors' own work. Interconnecting Heterogeneous Information Systems is suitable as a textbook for a graduate-level course on Interconnecting Heterogeneous Information Systems, as well as a secondary text for a graduate-level course on database or information systems, and as a reference for researchers and practitioners in industry.

Author : Vikram Jain
Publisher : Springer Nature
Page : 199 pages
File Size : 44,23 MB
Release : 2023-09-15
Category : Technology & Engineering
ISBN : 3031382307

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This book explores and motivates the need for building homogeneous and heterogeneous multi-core systems for machine learning to enable flexibility and energy-efficiency. Coverage focuses on a key aspect of the challenges of (extreme-)edge-computing, i.e., design of energy-efficient and flexible hardware architectures, and hardware-software co-optimization strategies to enable early design space exploration of hardware architectures. The authors investigate possible design solutions for building single-core specialized hardware accelerators for machine learning and motivates the need for building homogeneous and heterogeneous multi-core systems to enable flexibility and energy-efficiency. The advantages of scaling to heterogeneous multi-core systems are shown through the implementation of multiple test chips and architectural optimizations.

Author : David R. Kaeli
Publisher : Morgan Kaufmann
Page : 330 pages
File Size : 28,73 MB
Release : 2015-06-18
Category : Computers
ISBN : 0128016493

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Heterogeneous Computing with OpenCL 2.0 teaches OpenCL and parallel programming for complex systems that may include a variety of device architectures: multi-core CPUs, GPUs, and fully-integrated Accelerated Processing Units (APUs). This fully-revised edition includes the latest enhancements in OpenCL 2.0 including: • Shared virtual memory to increase programming flexibility and reduce data transfers that consume resources • Dynamic parallelism which reduces processor load and avoids bottlenecks • Improved imaging support and integration with OpenGL Designed to work on multiple platforms, OpenCL will help you more effectively program for a heterogeneous future. Written by leaders in the parallel computing and OpenCL communities, this book explores memory spaces, optimization techniques, extensions, debugging and profiling. Multiple case studies and examples illustrate high-performance algorithms, distributing work across heterogeneous systems, embedded domain-specific languages, and will give you hands-on OpenCL experience to address a range of fundamental parallel algorithms. Updated content to cover the latest developments in OpenCL 2.0, including improvements in memory handling, parallelism, and imaging support Explanations of principles and strategies to learn parallel programming with OpenCL, from understanding the abstraction models to thoroughly testing and debugging complete applications Example code covering image analytics, web plugins, particle simulations, video editing, performance optimization, and more

Author : Mohamed Ibnkahla
Publisher : CRC Press
Page : 551 pages
File Size : 28,24 MB
Release : 2017-12-19
Category : Technology & Engineering
ISBN : 1351835742

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Adaptive techniques play a key role in modern wireless communication systems. The concept of adaptation is emphasized in the Adaptation in Wireless Communications Series through a unified framework across all layers of the wireless protocol stack ranging from the physical layer to the application layer, and from cellular systems to next-generation wireless networks. This specific volume, Adaptive Signal Processing in Wireless Communications is devoted to adaptation in the physical layer. It gives an in-depth survey of adaptive signal processing techniques used in current and future generations of wireless communication systems. Featuring the work of leading international experts, it covers adaptive channel modeling, identification and equalization, adaptive modulation and coding, adaptive multiple-input-multiple-output (MIMO) systems, and cooperative diversity. It also addresses other important aspects of adaptation in wireless communications such as hardware implementation, reconfigurable processing, and cognitive radio. A second volume in the series, Adaptation and Cross-layer Design in Wireless Networks(cat no.46039) is devoted to adaptation in the data link, network, and application layers.