[PDF] Clock Generator Circuits For Low Power Heterogeneous Multiprocessor Systems On Chip eBook

Author : Amr Fahim
Publisher : Springer Science & Business Media
Page : 257 pages
File Size : 34,82 MB
Release : 2005-12-06
Category : Technology & Engineering
ISBN : 1402080808

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This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.

Author : Deog-Kyoon Jeong
Publisher :
Page : 304 pages
File Size : 42,80 MB
Release : 1989
Category : Integrated circuits
ISBN :

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Microprocessors based on RISC (Reduced Instruction Set Computer) concepts have demonstrated an ability to provide more computing power at a given level of integration than conventional microprocessors. The next step is multiprocessors is critic al in achieving efficient hardware utilization. This thesis focuses on the communication capability of VLSI circuits and presents new circuit techniques as a guide to build an interconnection network of VLSI microprocessors. Two of the most prominent problems in a synchronous system, which most of the current computer systems are based on, have been clock skew and synchronization failure. A new concept called self-timed systems solves such problems but has not been accepted i n microprocessor implementations yet because of its complex design procedure and increased overhead. With this in mind, this thesis concentrated on a system in which individual synchronous subsystems are connected asynchronously. Synchronous subsystems op erate with a better control over clock skew using a phase locked loop (PLL) technique. Communication among subsystems is done asynchronously with a controlled synchronization failure rate. One advantage is that conventional VLSI design methodologies which are more efficient can still be applied. Circuit techniques for PLL-based clock generation are described along with stability criteria. The main objective of the circuit is to realize a zero delay buffer. Experimental results show the feasability of such circuits in VLSI. Synchronizer circuit co nfigurations in both bipolar and MOS technology that best utilize each device, or overcome the technology limit using a bandwidth doubling technique are shown. Interface techniques including handshake mechanisms in such a system are also described. These techniques are applied in designing a memory management unit and cache controller (MMU/CC) for a multiprocessor workstation, SPUR. A SPUR workstation is an example of synchronous subsystems cluster with independent clock frequency. The interface and communication aspect of the overall system are revealed through the description of the MMU/CC. The VLSI chip is implemented in 1.6 um CMOS technology with 68,000 transistors.

Author : Kokula Krishna Hari K
Publisher : Association of Scientists, Developers and Faculties (ASDF)
Page : 257 pages
File Size : 18,13 MB
Release : 2015-08-10
Category : Computers
ISBN : 8192986616

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ICSSCCET 2015 will be the most comprehensive conference focused on the various aspects of advances in Systems, Science, Management, Medical Sciences, Communication, Engineering, Technology, Interdisciplinary Research Theory and Technology. This Conference provides a chance for academic and industry professionals to discuss recent progress in the area of Interdisciplinary Research Theory and Technology. Furthermore, we expect that the conference and its publications will be a trigger for further related research and technology improvements in this important subject. The goal of this conference is to bring together the researchers from academia and industry as well as practitioners to share ideas, problems and solutions relating to the multifaceted aspects of Interdisciplinary Research Theory and Technology.

Author : Naresh Maheshwari
Publisher : Springer Science & Business Media
Page : 210 pages
File Size : 41,13 MB
Release : 1998-10-31
Category : Technology & Engineering
ISBN : 9780792383215

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Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: Algorithms for sequential timing analysis Fast algorithms for clock skew optimization and their applications Efficient techniques for retiming large sequential circuits Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

Author : Behzad Razavi
Publisher : John Wiley & Sons
Page : 516 pages
File Size : 11,46 MB
Release : 1996-04-18
Category : Technology & Engineering
ISBN : 9780780311497

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Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.

Author : Ofer Shacham
Publisher : Stanford University
Page : 190 pages
File Size : 50,5 MB
Release : 2011
Category :
ISBN :

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Recent changes in technology scaling have made power dissipation today's major performance limiter. As a result, designers struggle to meet performance requirements under stringent power budgets. At the same time, the traditional solution to power efficiency, application specific designs, has become prohibitively expensive due to increasing nonrecurring engineering (NRE) costs. Most concerning are the development costs for design, validation, and software for new systems. In this thesis, we argue that one can harness ideas of reconfigurable designs to build a design framework that can generate semi-custom chips --- a Chip Generator. A domain specific chip generator codifies the designer knowledge and design trade-offs into a template that can be used to create many different chips. Like reconfigurable designs, these systems fix the top level system architecture, amortizing software and validation and design costs, and enabling a rich system simulation environment for application developers. Meanwhile, below the top level, the developer can "program" the individual inner components of the architecture. Unlike reconfigurable chips, a generator "compiles" the program to create a customized chip. This compilation process occurs at elaboration time --- long before silicon is fabricated. The result is a framework that enables more customization of the generated chip at the architectural level, because additional components and logic can be added if the customization process requires it. At the same time this framework does not introduce inefficiency at the circuit level because unneeded circuit overheads are not taped out. Using Chip Generators, we argue, will enable design houses to design a wide family of chips using a cost structure similar to that of designing a single chip --- potentially saving tens of millions of dollars --- while enabling per-application customization and optimization.

Author : Kunio Uchiyama
Publisher : Springer Science & Business Media
Page : 234 pages
File Size : 16,3 MB
Release : 2012-04-23
Category : Technology & Engineering
ISBN : 1461402840

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To satisfy the higher requirements of digitally converged embedded systems, this book describes heterogeneous multicore technology that uses various kinds of low-power embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and greater flexibility and superior performance per watt can then be achieved. This book defines the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. The authors developed three multicore chips (called RP-1, RP-2, and RP-X) according to the defined architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. Provides readers an overview and practical discussion of heterogeneous multicore technologies from both a hardware and software point of view; Discusses a new, high-performance and energy efficient approach to designing SoCs for digitally converged, embedded systems; Covers hardware issues such as architecture and chip implementation, as well as software issues such as compilers, operating systems, and application programs; Describes three chips developed according to the defined heterogeneous multicore architecture, including chip implementations, software environments, and working applications.

Author : Ragh Kuttappa
Publisher :
Page : 164 pages
File Size : 27,86 MB
Release : 2021
Category : Application-specific integrated circuits
ISBN :

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Modern integrated circuits are becoming more heterogeneous both in terms of technology and architecture. With the increase in number of cores and design complexity, there is an increasing need for energy efficient hardware solutions. Along with the increasing complexity of the architecture, the power consumption of the clock distribution network in integrated circuits is continuously increasing. Resonant clocking has been studied as an alternative solution to conventional clock distribution networks. Resonant rotary clocks is a type of resonant clocking which works on the adiabatic switching principles, providing complete solution for on-chip clock generation and distribution for low-power and low-skew clock network designs for high-performance synchronous architectures. In this dissertation, an ASIC compliant resonant rotary clocking synthesis methodology is developed to integrate novel algorithms and low-power solutions to enable: 1) scalable, and 2) shareable resonant clocking architecture. Resonant rotary clocks are designed to provide a low-power unitary clock domain solution across an individual die and multiple dies. The resonant rotary clocks are used to provide robust clock signals for high-speed interface circuits across a package. In addition, the resonant rotary clocks are used to provide multiphase clock signals to on-chip voltage regulators. The proposed solutions are compared to conventional clock distribution designs designed with phase locked loops (PLL) to demonstrate power savings, reliability, and area savings.