[PDF] Dual Mode Logic For Function Independent Fault Testing eBook
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A method of using hardware redundancy to ease the problem of fault testing in combinational and sequential logic circuits is presented. Dual-mode logic gates are used to construct combinational logic circuits which can be tested for all single stuck-at faults using just two function-independent tests. Analogous results for sequential circuits are also presented. (Author).
Fault-tolerant computing has evolved into a broad discipline, one that encompasses all aspects of reliable computer design. Diverse areas of fault-tolerant study range from failure mechanisms in integrated circuits to the design of robust software. Fault-tolerant computing is driven by a number of key factors, including ultra-high reliability, reduced life-cycle costs, and long-life applications. This book is intended to be both introductory and suitable for advanced-level graduates. Chapters can be selected in various combinations to provide courses with different orientations.
Comprehensive coverage of all aspects of space application oriented fault tolerance techniques • Experienced expert author working on fault tolerance for Chinese space program for almost three decades • Initiatively provides a systematic texts for the cutting-edge fault tolerance techniques in spacecraft control computer, with emphasis on practical engineering knowledge • Presents fundamental and advanced theories and technologies in a logical and easy-to-understand manner • Beneficial to readers inside and outside the area of space applications
Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. Practical problems at the end of each chapter for students.