[PDF] Bandwidth Sensitive Oblivious Routing eBook

Author : Tina Wen
Publisher :
Page : 83 pages
File Size : 16,40 MB
Release : 2009
Category :
ISBN :

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Traditional oblivious routing algorithms either do not take into account the bandwidth demand, or assume that each flow has its own private channel to guarantee deadlock freedom. Though adaptive routing schemes can react to varying network traffic, they require complicated router designs. In this thesis, we present a polynomial-time heuristic routing algorithm that takes bandwidth requirements of each flow into account to minimize maximum channel load. The heuristic algorithm has two variants. The first one produces a deadlock-free route. The second one produces a minimal route, and is deadlock-free with two or more virtual channels assuming proper VC allocation. Both routing algorithms are oblivious, and need only simple router designs. The performance of each bandwidth-sensitive routing algorithm is evaluated against dimension-order routing and against the other on a number of benchmarks.

Author : Keun Sup Shim
Publisher :
Page : 67 pages
File Size : 49,47 MB
Release : 2010
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ISBN :

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Most routers in on-chip interconnection networks (OCINs) have multiple virtual channels (VCs) to mitigate the effects of head-of-line blocking. Multiple VCs necessitate VC allocation schemes since packets or flows must compete for channels when there are more flows than virtual channels at a link. Conventional dynamic VC allocation, however, raises two critical issues. First, it still suffers from a fair amount of head-of-line blocking since all flows can be assigned to any VC within a link. Moreover, dynamic VC allocation compromises the guarantee of in-order delivery even when used with basic variants of dimension-ordered routing, requiring large reorder buffers at the destination core or, alternatively, expensive retransmission logic. In this thesis, we present two virtual channel allocation schemes to address these problems: Static Virtual Channel Allocation and Exclusive Dynamic Virtual Channel Allocation (EDVCA). Static VC allocation assigns channels to flows by precomputation when oblivious routing is used, and ensures deadlock freedom for arbitrary minimal routes when two or more VCs are available. EDVCA, on the other hand, is done at runtime, not requiring knowledge of traffic patterns or routes in advance. We demonstrate that both static VCA and EDVCA guarantee in-order packet delivery under single path routing, and furthermore, that they both outperform dynamic VC allocation (out-of-order) by effectively reducing head-of-line blocking. We also introduce a novel bandwidth-sensitive oblivious routing scheme (BSORM), which is deadlock-free through appropriate static VC allocation. Implementation for these schemes requires only minor, inexpensive changes to traditional oblivious dimension-ordered router architectures, more than offset by the removal of packet reorder buffers and logic.

Author : Michel A. Kinsy
Publisher :
Page : 71 pages
File Size : 28,78 MB
Release : 2009
Category :
ISBN :

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(Cont.) This thesis examines oblivious routing schemes for NoC architectures. It introduces various non-minimal, oblivious routing algorithms that globally allocate network bandwidth for a given application when estimated bandwidths for data transfers are provided, while ensuring deadlock freedom with no significant additional hardware. The work presents and evaluates these oblivious routing algorithms which attempt to minimize the maximum channel load (MCL) across all network links in an effort to maximize application throughput. Simulation results from popular synthetic benchmarks and concrete applications, such as an H.264 decoder, show that it is possible to achieve better performance than traditional deterministic and oblivious routing schemes.

Author : Dipika Darshana
Publisher :
Page : 54 pages
File Size : 30,92 MB
Release : 2008
Category : Ad hoc networks (Computer networks)
ISBN :

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Wireless ad hoc network consists of inexpensive nodes that form a mobile communication network. Due to limitations of the transmission range, the nodes rely on each other to forward packets such that messages can be delivered across the network. The selection of the path along which a packet is forwarded from the source node to the destination node is done by the routing algorithm. Most commonly used routing algorithms, though effective for non-real time applications, cannot handle real-time applications that require strict delay bounds on packet delivery. In this thesis, we propose a routing protocol that ensures timely delivery of real time data packets. The idea is to route packets in such a way that irrespective of factors like traffic load and node density, the average delay remains within acceptable bounds. This is done by carefully accessing the resources available to a route before a session is admitted along that route. Each link in the route is checked for sufficient bandwidth not only for the new session to be admitted but also for the sessions that are already using that link. The new session is admitted only if the admission does not violate the delay bounds of any on-going sessions. This method of route selection coupled with per-hop link reservations allows us to provide bounds on the delay performance. Extensive simulation experiments have been conducted that demonstrate the performance of the proposed routing protocol in terms of throughput, session blocking probability, packet drop probability, average path length, and delay.

Author : Jose Duato
Publisher : Elsevier
Page : 625 pages
File Size : 38,26 MB
Release : 2002-08-06
Category : Computers
ISBN : 0080508995

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The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature. * Gives a coherent, comprehensive treatment of the entire field* Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs* Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks* Focuses on issues critical to designers

Author : Soonhoi Ha
Publisher : Springer
Page : 0 pages
File Size : 46,38 MB
Release : 2017-10-11
Category : Technology & Engineering
ISBN : 9789401772662

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This handbook presents fundamental knowledge on the hardware/software (HW/SW) codesign methodology. Contributing expert authors look at key techniques in the design flow as well as selected codesign tools and design environments, building on basic knowledge to consider the latest techniques. The book enables readers to gain real benefits from the HW/SW codesign methodology through explanations and case studies which demonstrate its usefulness. Readers are invited to follow the progress of design techniques through this work, which assists readers in following current research directions and learning about state-of-the-art techniques. Students and researchers will appreciate the wide spectrum of subjects that belong to the design methodology from this handbook.

Author : Torsten Braun
Publisher : Springer Science & Business Media
Page : 277 pages
File Size : 16,38 MB
Release : 2008-08-02
Category : Computers
ISBN : 3540791205

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This book, one of the first of its kind, presents mechanisms, protocols, and system architectures needed to attain end-to-end Quality of Service over heterogeneous wired and wireless networks in the Internet.

Author : Prithviraj Banerjee
Publisher : CRC Press
Page : 260 pages
File Size : 37,51 MB
Release : 1995-08-08
Category : Computers
ISBN : 9780849326158

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This set of technical books contains all the information presented at the 1995 International Conference on Parallel Processing. This conference, held August 14 - 18, featured over 100 lectures from more than 300 contributors, and included three panel sessions and three keynote addresses. The international authorship includes experts from around the globe, from Texas to Tokyo, from Leiden to London. Compiled by faculty at the University of Illinois and sponsored by Penn State University, these Proceedings are a comprehensive look at all that's new in the field of parallel processing.